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| m68hc08 microcontrollers freescale.com mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet mc68hc908kx8 rev. 2.1 07/2005
mc68hc908kx8 ? mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com revision history mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) april, 2001 0.1 label for pin 9 corrected in figure 1-1 and figure 1-2 19, 20 $ff is the erase state of t he flash, not $00. 82, 252, 255 first bulleted paragraph under the subsection 15.5 interrupts reworded for clarity 177 revision to the description of the chx max bit and the note that follows that description 183 forced monitor mode information added to table 16-1. 192 in figure 16-10. monitor data format, resistor value for connection between vtst and irq1 changed from 10 k ? to 1 k ? . 194 february, 2002 1.0 7.2 features ? corrected third bullet 71 7.7.3 icg trim register ? corrected description of the trim7:trim0 bits 97 14.2 features ? corrected divide by factors in first bullet 165 figure 14-1. timebase block diagram ? corrected divide-by-2 blocks 166 table 14-1. timebase divider selection ? corrected last divider tap entry 167 section 15. timer interface module (tim) ? timer discrepancies corrected throughout this section 169 17.4 thermal characteristics ? corrected soic thermal resistance and maximum junction temperature 202 17.5 5.0-vdc dc electrical characteri stics and ? corrected footnote for vdd supply current in stop mode 203 and 204 appendix b. mc68hc08kx8 ? added to supply exception information for the mc68hc08kx8 215 march, 2004 2.0 reformatted to current publication standards throughout 2.7 flash page erase oper ation ? updated procedure 33 2.8 flash mass erase operation ? updated procedure 33 2.9 flash program/read operation ? updated procedure 34 figure 5-1. cop block diagram ? updated figure 53 table 6-1. instruction set summary ? added wait instruction 69 section 7. internal clock generator module (icg) ? updated with new information 71 through 98 14.2 features ? corrected values given in the first bullet 165 table 15-3. mode, edge, and level selection ? reworked for clarity 182 17.11 memory characteristics ? updated table with new information 210 july, 2005 2.1 updated to meet freescale identity guidelines. throughout mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 3 analog-to-digital co nverter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 chapter 4 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 5 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 6 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 7 internal clock generator modu le (icg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 8 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 chapter 9 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 10 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 11 input/output (i/o) po rts (ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 chapter 12 serial communications in terface module (sci) . . . . . . . . . . . . . . . . . . . . . . .111 chapter 13 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 chapter 14 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 chapter 15 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 chapter 16 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 chapter 17 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 chapter 18 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 193 appendix a mc68hc908kx2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 appendix b mc68hc08kx8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 list of chapters mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 6 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4.1 supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4.3 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4.4 port a input/output (i/o) pins (pta4/kbd4 ?pta0/kbd0 ) . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4.5 analog reference pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4.6 port b input/output (i/o) pins (ptb7/(osc2)/rst ?ptb0/ad0) . . . . . . . . . . . . . . . . . . . . . 21 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7 flash page erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 2.10 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.11 flash block protect register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.12 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.13 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 8 freescale semiconductor 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.1 adc analog power and adc voltage reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.2 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 4 configuration register (config) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 5 computer operating properly module (cop) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 chapter 6 central processor unit (cpu) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 9 6.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 7 internal clock g enerator module (icg) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.1 clock enable circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2 internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.2.2 modulo "n" divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.2.3 frequency comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.3.2.4 digital loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.3 external clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.3.1 external oscillator amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.3.2 external clock input path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.4 clock monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3.4.1 clock monitor reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3.4.2 internal clock activity detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.4.3 external clock activity detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.5 clock selection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.3.5.1 clock selection switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.5.2 clock switching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.4 usage notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.4.1 switching clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.4.2 enabling the clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.4.3 using clock monitor interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.4 quantization error in dco output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4.4.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4.4.2 binary weighted divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4.4.3 variable-delay ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.4.4 ring oscillator fine-adjust circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.5 switching internal clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.6 nominal frequency settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.6.1 settling to within 15% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.6.2 total settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.7 trimming frequency on the internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table of contents mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 10 freescale semiconductor 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.6 config (or mor) register options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.6.1 external clock enable (extclken) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.6.2 external crystal enable (extxtalen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.6.3 slow external clock (extslow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.4 oscillator enable in stop (oscenin stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.7.1 icg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.2 icg multiplier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.3 icg trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.7.4 icg dco divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.7.5 icg dco stage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 chapter 8 external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4 irq1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.5 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 chapter 9 keyboard interrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.6 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.6.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.6.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 chapter 10 low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.3.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.3.4 lvi trip selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 11 10.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 chapter 11 input/output (i/o) ports (ports) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.2.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 11.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 chapter 12 serial communications in terface module (sci) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 12.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table of contents mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 12 freescale semiconductor 12.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.7.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.7.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.7.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.7.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.7.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.7.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.7.7 sci baud rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 chapter 13 system integrati on module (sim) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3.1 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3.1.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3.1.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3.1.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3.1.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.3.1.5 forced monitor mode entry reset (menrst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.3.1.6 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 42 13.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 13.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7.1 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7.2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.7.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.7.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.7.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 13 chapter 14 timebase module (tbm) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.5 tbm interrupt rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.7 timebase control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 chapter 15 timer interface module (tim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.4.4 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 59 15.4.5 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.4.6 pulse-width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.4.7 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.4.8 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.4.9 pwm initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 63 15.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.8.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 15.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 chapter 16 development support 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.2.1.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 table of contents mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 14 freescale semiconductor 16.2.1.3 tim1 and tim2 during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.2.1.4 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 71 16.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 16.2.2.3 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 16.2.2.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2.2.5 break auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.3 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3.1.1 monitor mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3.1.2 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3.1.3 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.3.1.4 monitor mode vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.3.1.5 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.1.6 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.1.7 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.1.8 force monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.1.9 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.1.10 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 chapter 17 electrical specifications 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.5 5.0-vdc dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 17.6 3.0-vdc dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.7 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 17.8 external oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 17.9 trimmed accuracy of the internal clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.9.1 2.7-volt to 3.3-volt trimmed internal clock gener ator characteristics . . . . . . . . . . . . . . . 188 17.9.2 4.5-volt to 5.5-volt trimmed internal clock gener ator characteristics . . . . . . . . . . . . . . . 188 17.10 analog-to-digital converter (adc) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 mc68hc908kx8 ? mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 15 chapter 18 ordering information and m echanical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.3 16-pin plastic dual in-line package (pdip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 18.4 16-pin small outline package (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 appendix a mc68hc908kx2 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 a.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 appendix b mc68hc08kx8 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 b.2 flash x rom module changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 b.2.1 flash for rom substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 b.2.2 partial use of flash-related module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 b.3 configuration register programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 b.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 b.4.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 b.4.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 b.4.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 b.4.4 5.0-vdc dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 b.4.5 3.0-vdc dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 b.4.6 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 b.4.7 external oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 b.4.8 trimmed accuracy of the internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 b.4.8.1 2.7-volt to 3.3-volt trimmed internal clock g enerator characteristics . . . . . . . . . . . . . 206 b.4.8.2 4.5-volt to 5.5-volt trimmed internal clock g enerator characteristics . . . . . . . . . . . . . 206 b.4.9 analog-to-digital converter (adc) ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 b.4.10 memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table of contents mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 16 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc908kx8 is a member of the low-cos t, high-performance m68hc08 family of 8-bit microcontroller units (mcu). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modul es, memory sizes and types, and package types. the information contained is this document pertains to the mc68hc908kx2 and the mc68hc08kx8 with the exceptions found in: appendix a mc68hc908kx2 appendix b mc68hc08kx8 1.2 features features include: high-performance m68hc08 architecture fully upward-compatible object code wi th m6805, m146805, and m68hc05 families maximum internal bus frequencies of: ? 8 mhz at 5.0 v ? 4 mhz at 3.0 v internal oscillator requiring no external components: ? software selectable bus frequencies ? 25 percent accuracy with trim capability to 2 percent ? clock monitor ? option to allow use of external clock sour ce or external crystal/ceramic resonator eight kbytes of on-chip, in-circuit programmable flash memory flash program memory security (1) on-chip programming firmware for use with hos t personal computer which does not require high voltage for entry 192 bytes of on-chip random-access memory (ram) 16-bit, 2-channel timer interface (tim) module 4-channel, 8-bit, analog-to-digital converter (adc) with high-voltage reference (v refh ) double bonded to v dd pin 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. general description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 18 freescale semiconductor serial communications interface (sci) module 5-bit keyboard interrupt (kbi) with wakeup feature 13 general-purpose input/output (i/o) ports: ? five shared with kbi and tim, with 15-m a source/15-ma sink capabilities and with programmable pullups on gener al- purpose input ports ? four shared with adc ? two shared with sci low-voltage inhibit (lvi) module with software sele ctable trip points, 2.6-v or 4.3-v trip point timebase module (tbm) with ? clock prescaler for eight user-selec table, periodic real-time interrupts ? active clock source in stop mode for periodic wakeup from stop using external crystal or internal oscillator external asynchronous interrupt pin with internal pullup (irq1 ) system protection features: ? computer operating properly (cop) reset ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset 16-pin plastic dual in-line (pdip) or small outline (soic) package low-power design fully static with stop and wait modes internal power-up reset circuit requiring no external pins ?40 c to +125 c operation features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes, eight more than the m68hc05 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908kx8. mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 19 mcu block diagram figure 1-1. mc68hc908kx8 mcu block diagram computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module general description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 20 freescale semiconductor 1.4 pin assignments figure 1-2 shows the pin assignments for mc68hc908kx8. figure 1-2. pdip and soic pin assignments 1.4.1 supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to prov ide power supply bypassing at the mcu as shown in figure 1-3 . place the bypass capacitors as close to the mcu power pins as possible. use high-frequency response ceramic capacitors for c bypass . c bulk are optional bulk current bypass capacitors for use in applications that require the port pi ns to source high-current levels. figure 1-3. power supply bypassing v ss pta1/kbd1 pta0/kbd0 irq1 ptb0/ad0 ptb1/ad1 ptb2/ad2 ptb3/ad3 ptb7/(osc2)/rst ptb6/(osc1) ptb5/txd ptb4/rxd pta2/kbd2 /tch0 pta3/kbd3 /tch1 pta4/kbd4 v dd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 mcu v dd c bulk c bypass 0.1 f v ss v dd + note: component values shown represent typical applications. pin assignments mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 21 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are available through programming op tions in the configuration register. these pins then become the connections to an external cloc k source or crystal/ceramic resonator. ptb7 and ptb6 are not available for the crystal/ceramic resona tor option and ptb6 is unavailable for the external clock source option. 1.4.3 external in terrupt pin (irq1 ) irq1 is an asynchronous external interrupt pin with an internal pullup resistor. see chapter 8 external interrupt (irq) . 1.4.4 port a input/out put (i/o) pins (pta4/kbd4 ?pta0/kbd0 ) pta4/kbd4 ?pta0/kbd0 is a 5-bit special-function port that s hares its pins with the keyboard interrupt (kbi) module and the 2-channe l timer module (tim). any or all of the port a pins can be programmed to serve as keyboard interrupt pins. the respective pin utilizes an internal pul lup resistor when enabled. see chapter 9 keyboard interrupt module (kbi) . each port a pin contains a software selectable internal pullup resistor when the general-function i/o port is configured as an input. see chapter 11 input/output (i/o) ports (ports) . the pullup resistor is automatically disabled once a tim special function is enabled for that pin. all port a pins are high-current source/sink pins. note any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908kx8 do not require termination, termination is recommended to reduce the possibility of static damage. 1.4.5 analog reference pin (v refh ) the v refh pin is the analog reference voltage for the analog-to-digital converter (adc) module. the voltage is supplied through a double-bond to the v dd pin. see chapter 17 electrical specifications for adc parameters. 1.4.6 port b input/output (i/o) pins (ptb7/(osc2)/rst ?ptb0/ad0) ptb7/(osc2)/rst ?ptb0/ad0 are general-purpose bidirectio nal i/o port pins, all sharing special functions. ptb7 and ptb6 share with the on-chip oscillat or circuit through configuration options. see 7.3.3 external clock generator . ptb5 and ptb4 share with the sci module. see chapter 12 serial communications interface module (sci) . ptb3?ptb0 share with the adc module. see chapter 3 analog-to-digital converter (adc) . general description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 22 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 23 chapter 2 memory 2.1 introduction the central processor unit (cpu08) can a ddress 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 7680 bytes of flash memory 192 bytes of random-access memory (ram) 36 bytes of user-defined vectors 295 bytes of monitor read-only memory (rom) 2.2 i/o registers most of the control, status, and data registers are in the zero-page area of $0000?$003f. additional input/output (i/o) registers have the following addresses: $fe01 ? sim reset status register, srsr $fe04 ? interrupt status register 1, int1 $fe05 ? interrupt status register 2, int2 $fe06 ? interrupt status register 3, int3 $fe08 ? flash control register, flcr $fe09 ? break address register high, brkh $fe0a ? break address register low, brkl $fe0b ? break status and control register, brkscr $fe0c ? lvi status register, lvisr $ff7e ? flash block protect register, flbpr in non-volatile flash memory $ffff ? cop control register, copctl a summary of the available registers is provided in figure 2-2 . table 2-1 is a list of vector locations. 2.3 monitor rom the 295 bytes at addresses $fe20?$ff46 are reserved rom addresses that contain the instructions for the monitor functions. memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 24 freescale semiconductor $0000 $003f i/o registers (64 bytes) $fe00 reserved $fe01 sim reset status register (srsr) $fe02 reserved $0040 $00ff ram (192 bytes) $fe03 reserved $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $0100 $0fff unimplemented (3839 bytes) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $1000 $13ff flash burn-in rom (1024 bytes) $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $1400 $dfff unimplemented (52,224 bytes) $fe0c lvi status register (lvisr) $fe0d $fe1f unimplemented (18 bytes) $e000 $fdff user flash memory (7680 bytes) $fe20 $ff46 monitor rom (295 bytes) $ff47 $ff7d unimplemented (57 bytes) $ff7e flash block protect register (flbpr) $ff7f $ffdb unimplemented (90 bytes) $ffdc $ffff flash vectors (36 bytes) figure 2-1. memory map monitor rom mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 25 addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 106. read: 0 0 0 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 108. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 unimplemented $0003 unimplemented $0004 data direction register a (ddra) see page 106. read: 0 0 0 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 109. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 $000c unimplemented $000d port a input pullup enable register (ptapue) see page 108. read: 0 0 0 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e $0012 unimplemented $0013 sci control register 1 (scc1) see page 125. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) see page 127. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) see page 129. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) see page 130. read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 5) memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 26 freescale semiconductor $0017 sci status register 2 (scs2) see page 132. read:000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) see page 133. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 133. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a keyboard status and control register (kbscr) see page 99. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 100. read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c timebase control register (tbcr) see page 154. read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 $001d irq status and control register (iscr) see page 94. read:0000irqf10 imask1 mode1 write:rrrrrack1 reset:00000000 $001e configuration register 2 (1) (config2) see page 48. read: r 0 ext- xtalen ext- slow ext- clken 0 oscenin- stop scibdsrc write: reset:00000000 $001f configuration register 1 (1) (config1) see page 47. read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: por reset: other resets: 0 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 1. lvi5or3 is only writable after a power-on reset (por). bit 6 of config1 is read-only and will read 0. all other bits in config1 and config2 ar e one-time writable after any reset. $0020 timer status and control register (tsc) see page 163. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (tcnth) see page 164. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 5) monitor rom mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 27 $0022 timer counter register low (tcntl) see page 164. read:bit 7654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (tmodh) see page 165. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer counter modulo register low (tmodl) see page 165. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (tsc0) see page 165. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (tch0h) see page 168. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer channel 0 register low (tch0l) see page 168. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (tsc1) see page 165. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer channel 1 register high (tch1h) see page 168. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (tch1l) see page 168. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b $0035 unimplemented $0036 icg control register (icgcr) see page 87. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 1. see 7.7.1 icg control register for method of clearing the cmf bit. $0037 icg multiplier register (icgmr) see page 88. read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 5) memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 28 freescale semiconductor $0038 icg trim register (icgtr) see page 89. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 icg divider control register (icgdvr) see page 89. read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu $003a icg dco stage control register (icgdsr) see page 89. read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset:uuuuuuuu $003b reserved rrrrrrrr $003c analog-to-digital status and control register (adscr) see page 43. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 $003d analog-to-digital data register (adr) see page 45. read:ad7ad6ad5ad4ad3ad2ad1ad0 write:rrrrrrrr reset: indeterminate after reset $003e analog-to-digital input clock register (adclk) see page 45. read: adiv2 adiv1 adiv0 adiclk 000 r write: reset:00000000 $003f unimplemented $fe00 sim break status register (sbsr) (1) see page 172. read:000100bw0 write:rrrrrrnoter reset:00010000 1. writing a 0 clears bw. $fe01 sim reset status register (srsr) see page 148. read: por 0 cop ilop ilad menrst lvi 0 write: por:10000000 $fe02 break auxiliary register (brkar) see page 173. read:0000000 bdcop write: reset:00000000 $fe03 sim break flag control register (sbfcr) see page 173. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 149. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 5) monitor rom mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 29 $fe05 interrupt status register 2 (int2) see page 150. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 150. read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 $fe07 flash test control register (fltcr) read: rrrrrrrr write: reset: $fe08 flash control register (flcr) see page 31. read:0000 hven margin erase pgm write: reset:00000000 $fe09 break address register high (brkh) see page 172. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 172. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 171. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 103. read:lviout000000r write: reset:00000000 $ff7e flash block protect register (flbpr) (1) see page 36. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset 1. non-volatile flash register $ffff cop control register (copctl) see page 53. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 5) memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 30 freescale semiconductor table 2-1. vector locations address vector low $ffdc timebase module vector (high) $ffdd timebase module vector (low) $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) $ffe6 sci receive error vector (high) $ffe7 sci receive error vector (low) $ffe8 reserved $ffe9 reserved $ffea reserved $ffeb reserved $ffec reserved $ffed reserved $ffee reserved $ffef reserved $fff0 reserved $fff1 reserved $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) $fff8 cmireq vector (high) $fff9 cmireq vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) priority random-access memory (ram) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 31 2.4 random-access memory (ram) addresses $0040?$00ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805, m146805 and m68hc05compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or dur ing the interrupt stacking operation. 2.5 flash memory (flash) the flash memory is an array of 7,680 bytes with an additional 36 bytes of user vectors and one byte used for block protection. note an erased bit reads as 1 and a programmed bit reads as 0. the program and erase operations are facilitated thr ough control bits in the flash control register (flcr). see 2.6 flash control register . the flash is organized internally as an 8192-word by 8-bit complementary metal-oxide semiconductor (cmos) page erase, byte (8-bit) program embedded flash memory. each page consists of 64 bytes. the page erase operation erases all words within a page. a page is composed of two adjacent rows. a security feature prevents viewing of the flash contents. (1) 2.6 flash control register the flash control register (flcr) controls flash program and erase operations. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr) memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 32 freescale semiconductor hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can be set only if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the 8- kbyte flash array for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 2.7 flash page erase operation use this step-by-step procedure to erase a page (64 bytes) of flash memory to read as 1: 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note while these operations must be performed in the order shown, other unrelated operations may occur between the steps. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. flash mass erase operation mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 33 2.8 flash mass erase operation use the following procedure to erase the entire flash memory to read as a 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. 1. when in monitor mode, with security sequence failed (see 16.3.2 security ), write to the flash block protect register in- stead of any flash address. memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 34 freescale semiconductor 2.9 flash program/read operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $ xx60, $xx80, $xxa0, $xxc0, and $xxe0. use this step-by-step procedure to program a row of flash memory ( figure 2-4 is a flowchart representation). note only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desir ed bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. this program sequence is repeated throughout the memory until all data is programmed. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 17.11 memory characteristics . 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum. flash program/read operation mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 35 figure 2-4. flash programming flowchart set hven bit read the flash block write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv yes no end of programming the time between each flash address change (step 7 to step 7), must not exceed the maximum programming time, t prog maximum. or the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) notes: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algori thm assumes the row/s to be programmed are initially erased. protect register write data to the flash address to be programmed completed programming this row? memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 36 freescale semiconductor 2.10 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a bloc k of memory from unintentional erase or program operations due to system malfunction. this protection is done by using the flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when flbpr is programmed with all 0s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory address ranges as shown in 2.11 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. the flbpr itself can be erased or programmed only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from re set into the monitor mode. 2.11 flash block protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory, and therefore can be written only during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr7?bpr0 ? flash block protect bits these eight bits represent bits 13?6 of a 16-bit me mory address. bits 15 and 14 are 1s and bits 5?0 are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this star t address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be $xx00, $xx40, etc., (64 bytes page boundaries) within the flash memory. see figure 2-6 and table 2-2 . address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) wait mode mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 37 figure 2-6. flash block protect start address 2.12 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode. 2.13 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode note standby mode is the power-saving mode of the flash module in which all internal control signals to the flash are inactive and the current consumption of the flash is at a minimum. table 2-2. protect start address examples bpr7?bpr0 start of address of protect range (1) 1. the end address of the protected range is always $ffff. $80 the entire flash memory is protected. $81 ( 1000 0001 ) $e040 (111 0 0000 01 00 0000) $82 ( 1000 0010 ) $e080 (111 0 0000 10 00 0000) and so on... $fe ( 1111 1110 ) $ff80 (111 1 1111 10 00 0000) $ff the entire flash memory is not protected. 16-bit memory address start address of flash 1 flbpr value 000000 1 block protect memory mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 38 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 39 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the 8-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: four channels with multiplexed input linear successive approximation 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 3.3 functional description the adc provides four pins for samp ling external sources at pins ptb3 ? ptb0. an analog multiplexer allows the single adc converter to select one of four adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximatio n register-based counters. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . the mc68hc908kx8 uses v dd as the high voltage reference. 3.3.1 adc port i/o pins ptb3?ptb0 are general-purpose input/output (i/o) pi ns that are shared with the adc channels. the channel select bits define which adc channel/p ort pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as in put to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any effect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at 0. if the ddr bit is at 1, the value in the port data latch is read. mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 40 freescale semiconductor analog-to-digital converter (adc) figure 3-1. block diagram highlighting adc block and pins computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 41 figure 3-2. adc block diagram 3.3.2 voltage conversion when the input voltage to the adc equals v refh (see 17.9 trimmed accuracy of the internal clock generator ), the adc converts the signal to $ff (full scale). if the input voltage equals v ss, the adc converts it to $00. input voltages between v refh and v ss are a straight-line linear conversion. all other input voltages will result in $ff if greater than v refh and $00 if less than v ss . note input voltage should not exceed the high-voltage reference, which in turn should not exceed supply voltages. 3.3.3 conversion time conversion starts after a write to the adscr (adc status control register, $003c) and requires between 16 and 17 adc clock cycles to complete. conversion time in terms of the number of bus cycles is a function of cgmxclk frequency, bus frequency, the adiv prescaler bits, and the adiclk bit. for example, with a cgmxclk frequency of 8 mhz, bus frequency of 2 mhz, and fixed adc clock frequency of 1 mhz, one conversion will take between 16 and 17 s and there will be 32 bus cycles between each conversion. sample rate is approximately 60 khz. internal data bus reset interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x ptb ptbx ddrbx write read ddrb read ptb write ptb read adr analog-to-digital converter (adc) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 42 freescale semiconductor refer to 17.9 trimmed accuracy of th e internal clock generator . 3.3.4 continuous conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be over written whether that data has been read or not. conversions will continue until the adco bit (adc stat us control register, $003c) is cleared. the coco bit is set after the first conversion and will stay set until the next write of the adc status and control register or the next read of the adc data register. 3.3.5 accuracy and precision the conversion process is monotoni c and has no missing codes. see 17.9 trimmed accuracy of the internal clock generator for accuracy information. 3.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit (adc status control register, $003c) is at 0. if the coco bit is set, a direct-memory access (dma) interrupt is generated. note because the mc68hc908kx8 does not have a dma module, the coco bit should not be set while interrupts are enabled (aien = 1). the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the following subsections des cribe the low-power modes. 3.5.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register before executing the wait instruction. 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 16 to 17 adc clock cycles conversion time = ???????????? adc clock frequency number of bus cycles = conversion time x bus frequency i/o signals mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 43 3.6 i/o signals the adc module has four channels that ar e shared with port b pins. refer to 17.9 trimmed accuracy of the internal clock generator for voltages referenced here. 3.6.1 adc analog power and adc voltage reference pins the adc analog portion uses v dd as its power pin and v ss as its ground pin. due to pin limitations, the v refl signal is internally connected to v ss on the mc68hc908kx8. on the mc68hc908kx8, the v refh signal is internally connected to v dd . 3.6.2 adc voltage in (adcvin) adcvin is the input voltage signal from one of the four adc channels to the adc module. 3.7 i/o registers these i/o registers control and monitor adc operation: adc status and control register, adscr adc data register, adr adc clock register, adiclk 3.7.1 adc status and control register the following paragraphs describe the function of the adc status and control register (adscr). coco ? conversions complete bit when the aien bit is a 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and cont rol register is written or whenever the adc data register is read. when the aien bit is a 1, the adc module is c apable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit (adc status control register, $003c) is at 0. if the coco bit is at 1, a dma interrupt is generated. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupts enabled (aien = 1) note because the mc68hc908kx8 does not have a dma module, the coco bit should not be set while interrupts are enabled (aien = 1). address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 r= reserved figure 3-3. adc status and control register (adscr) analog-to-digital converter (adc) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 44 freescale semiconductor aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the adr register is read or the adscr register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conver sion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to select the input for the a/d measurement. the choices are one of four adc channels, as well as v refh and v ss . input selection is detailed in table 3-1 . care should be taken when using a port pi n as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when t he adc is not used. reset sets these bits. note recovery from the disabled state requi res one conversion cycle to stabilize. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 0 0 0 0 0 ptb0 0 0 0 0 1 ptb1 0 0 0 1 0 ptb2 0 0 0 1 1 ptb3 00100 unused (1) 1. if any unused channels are selected, th e resulting adc conversion will be unknown. ????? ? 11100 unused (1) 11101 v refh (2) 2. the voltage levels supplied from internal re ference nodes as specified in the table are used to verify the operation of t he adc converter both in production test and for user applica- tions. 11110 v ssad (2) 1 1 1 1 1 adc power off i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 45 3.7.2 adc data register one 8-bit result register is provided. this regi ster is updated each time an adc conversion completes. 3.7.3 adc input clock register this register selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which se lects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock confi gurations. the adc clock should be set to approximately 1 mhz. adiclk ? adc input clock select bit adiclk selects either bus clock or the oscillator output clock (cgmxclk) as the input clock source to generate the internal adc rate clock. reset selects cgmxclk as the adc clock source. 1 = internal bus clock 0 = oscillator output clock (cgmxclk) address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset: indeterminate after reset r= reserved figure 3-4. adc data register (adr) address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 000 r write: reset: 0 0000000 = unimplemented r = reserved figure 3-5. adc input clock register (adiclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care analog-to-digital converter (adc) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 46 freescale semiconductor the adc requires a clock rate of approximately 1 mhz for correct operation. if the selected clock source is not fast enough, the adc will generate incorrect conversions. see 17.9 trimmed accuracy of the internal clock generator . note during the conversion process, changi ng the adc clock will result in an incorrect conversion. f cgmxclk or bus frequency f adic = ???????????? ? 1 mhz adiv[2:0] mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 47 chapter 4 configuration register (config) 4.1 introduction this section describes the configuration registers, config1 and config2. the configuration registers control these options: stop mode recovery time, 32 cgmxclk cycles or 4096 cgmxclk cycles computer operating properly (cop) timeout period, 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles stop instruction computer operating properly (cop) module low-voltage inhibit (lvi) module control and voltage trip point selection enable/disable the oscillator (osc) during stop mode serial communications interface (sci) clock source selection external clock/crystal source control enable/disable for the flash charge-pump regulator 4.2 functional description the configuration registers are used in the initializa tion of various options and can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that these registers be written immediately after reset. the configuration registers are located at $001e and $001f. for compatibility, a write to a read-only memory (rom) version of the mcu at this location will have no effect. the configuration register may be read at anytime. note the config module is known as an mor (mask option register) on a rom device. on a rom device, the option s are fixed at the time of device fabrication and are neither writable nor changeable by the user. on a flash device, the config registers are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 4-1 and figure 4-2 . address: $001e bit 7654321bit 0 read: r 0 ext- xtalen ext- slow ext- clken 0 oscenin- stop scibd- src write: reset:00000000 = unimplemented r = reserved figure 4-1. configuration register 2 (config2) configuration register (config) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 48 freescale semiconductor extclken ? external clock enable bit extclken enables an external clock source or crystal /ceramic resonator to be used as a clock input. setting this bit enables ptb6/(osc1) pin to be a clock inpu t pin. clearing this bit (default setting) allows the ptb6/(osc1) and ptb7/(osc2)/rst pins to function as a general-purpose input/output (i/o) pin. refer to table 4-1 for configuration options for the external source. see chapter 7 internal clock generator module (icg) for a more detailed description of the external clock operation. 1 = allows ptb6/(osc1) to be an external clock connection 0 = ptb6/(osc1) and ptb7/(osc2)/rst function as i/o port pins (default). extslow ? slow external crystal enable bit the extslow bit has two functions. it configures the icg module for a fast (1 mhz to 8 mhz) or slow (30 khz to 100 khz) speed crystal. the option also configures the clock monitor operation in the icg module to expect an external freq uency higher (307.2 khz to 32 mhz) or lower (60 hz to 307.2 khz) than the base frequency of the internal oscillator. see chapter 7 internal clock generator module (icg) . 1 = icg set for slow external crystal operation 0 = icg set for fast external crystal operation extxtalen ? external crystal enable bit extxtalen enables the external oscillator circuits to be configured for a crystal configuration where the ptb6/(osc1) and ptb7/(osc2)/rst pins are the connections for an external crystal. note this bit does not function without setting the extclken bit also. address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 (1) ssrec stop copd write: reset:00000000 other resets:0000u000 1. the lvi5or3 bit is cleared only by a power-on reset (por). u = unaffected figure 4-2. configuration register 1 (config1) table 4-1. external clock option settings external clock configuration bits pin function description extclken extxtalen ptb6/(osc1) ptb7/(osc2)/rst 00 ptb6 ptb7 default setting ? external oscillator disabled 01 ptb6 ptb7 external oscillator disabled since extclken not set 10 osc1 ptb7 external oscillator configured for an external clock source input (square wave) on osc1 11 osc1 osc2 external oscillator configured for an external crystal configuration on osc1 and osc2. system will also operate with square-wave clock source in osc1. functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 49 clearing the extxtalen bit (default setting) allows the ptb7/(osc2)/rst pin to function as a general-purpose i/o pin. refer to table 4-1 for configuration options for the external source. see chapter 7 internal clock generator module (icg) for a more detailed description of the external clock operation. extxtalen, when set, also configures the clock moni tor to expect an external clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external cl ock stabilization divider in the clock monitor for a 4096-cycle timeout to allow the proper stabilizati on time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. 1 = allows ptb7/(osc2)/rst to be an external crystal connection. 0 = ptb7/(osc2)/rst functions as an i/o port pin (default). osceninstop ? oscillator enable in stop mode bit osceninstop, when set, will enable the internal clock generator module to continue to generate clocks (either internal, iclk, or external, eclk) in stop mode. see chapter 7 internal clock generator module (icg) . this function is used to keep the timebase running while the rest of the microcontroller stops. see chapter 14 timebase module (tbm) . when clear, all clock generation will cease and both iclk and eclk will be forced low during stop mode. th e default state for this option is clear, disabling the icg in stop mode. 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode (default) note this bit has the same functionality as the oscstopenb config bit in mc68hc908gp20 and mc68hc908gr8 parts. scibdsrc ? sci baud rate clock source bit scibdsrc controls the clock source used for the sc i. the setting of this bit affects the frequency at which the sci operates. 1 = internal data bus clock is used as clock source for sci. 0 = cgmxclk is used as clock source for sci. coprs ? cop rate select bit copd selects the cop timeout period. reset clears coprs. see chapter 5 computer operating properly module (cop) . 1 = cop timeout period = 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 ? 2 4 cgmxclk cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see chapter 10 low-voltage inhibit (lvi) . 1 = lvi module resets disabled 0 = lvi module resets enabled configuration register (config) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 50 freescale semiconductor lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 10 low-voltage inhibit (lvi) . 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module (see see chapter 10 low-voltage inhibit (lvi) .). the voltage mode selected for the lvi should match the operating v dd . see chapter 17 electrical specifications for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode. 0 = lvi operates in 3-v mode. note the lvi5or3 bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclck cycles note exiting stop mode by an lvi reset will result in the long stop recovery. if the system clock source selected is the inte rnal oscillator or the external crystal and the osceninstop configuration bit is not set, the oscill ator will be disabled during stop mode. the short stop recovery does not provide enough time for osci llator stabilization and thus the ssrec bit should not be set. when using the lvi during normal operation but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 cgmxclk cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configuration option, the 32-cgmxclk delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 5 computer operating properly module (cop) . 1 = cop module disabled 0 = cop module enabled mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 51 chapter 5 computer operating properly module (cop) 5.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software to recover from a runaway code. periodically clearing the cop counter will prevent a cop reset from occurring. the cop module can be disabled through the copd bit in the configuration (config) register. 5.2 block diagram figure 5-1. cop block diagram copctl write busclkx4 reset vector fetch sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter computer operating properly module (cop) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 52 freescale semiconductor 5.3 functional description the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 13 ?2 4 or 2 18 ?2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the configuration register. with a 2 18 ?2 4 cgmxclk cycle overflow option, a 4.9152- mhz cgmxclk frequency gives a cop timeout period of 53.3 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 5?12 of the prescaler. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls an internal reset for 64 cgmxclk cycles and sets the cop bit in the system integration module (sim) reset status register (srsr). in monitor mode, the cop is disabled if the irq1 pin is held at v tst . note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 5.4 i/o signals the following paragraphs describe the signals shown in figure 5-1 . 5.4.1 cgmxclk cgmxclk is the internal clock generator (icg) module?s oscillator output signal. cgmxclk is selected from either the internal clock source or the external crystal. 5.4.2 stop instruction the stop instruction clears the cop prescaler. 5.4.3 copctl write writing any value to the cop control register (c opctl) clears the cop counter and clears stages 12?5 of the cop prescaler. reading the cop control register returns the low byte of the reset vector. 5.4.4 powe r-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 5.4.5 internal reset an internal reset clears the cop prescaler and the cop counter. cop control register mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 53 5.4.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 5.4.7 copd (cop disable) the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. see chapter 4 configuration register (config) . 5.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register. see chapter 4 configuration register (config) . 5.5 cop control register the cop control register (copctl) is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and stages 12?5 of the cop prescaler and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 5.6 interrupts the cop does not generate cpu interrupt requests. 5.7 monitor mode the cop is disabled in monitor mode when v tst is present on the irq1 pin. 5.8 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 5.8.1 wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 5-2. cop control register (copctl) computer operating properly module (cop) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 54 freescale semiconductor 5.8.2 stop mode stop mode holds the 12-bit prescaler counter in re set until after stop mode is exited. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration has the stop instruction disabled, execution of a stop instruction results in an illegal opcode reset. mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 55 chapter 6 central processor unit (cpu) 6.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 6.3 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 56 freescale semiconductor figure 6-1. cpu registers 6.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 6.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 57 6.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc) central processor unit (cpu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 58 freescale semiconductor 6.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 59 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 6.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 6.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 60 freescale semiconductor 6.7 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. table 6-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c instruction set summary mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 61 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 6-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 62 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc instruction set summary mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 63 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 6-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 64 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c opcode map mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 65 6.8 opcode map see table 6-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 6-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 66 freescale semiconductor central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 67 chapter 7 internal clock generator module (icg) 7.1 introduction the internal clock generator module (icg) is used to cr eate a stable clock source for the microcontroller without using any external components. the icg gener ates the oscillator output clock (cgmxclk), which is used by the computer operating properly (cop), low-voltage inhibit (lvi), and other modules. the icg also generates the clock generator output (cgmout), which is fed to the system integration module (sim) to create the bus clocks. the bus fr equency will be one-fourth the frequency of cgmxclk and one-half the frequency of cgmout. finally, the icg generates the timebase clock (tbmclk), which is used in the timebase module (tbm). 7.2 features features of the icg include: selectable external clock generator, either one pin ex ternal source or two pin crystal, multiplexed with port pins internal clock generator with programmable frequenc y output in integer multiples of a nominal frequency (307.2 khz 25%) frequency adjust (trim) regist er to improve variability to 2% bus clock software selectable from either inter nal or external clock (bus frequency range from 76.8 khz 25% to 9.75 mhz 25% in 76.8 khz increments ? note that for the mc68hc908kx8, mc68hc908kx2, and mc68hc08kx8, do not exceed the maximum bus frequency of 8 mhz at 5.0 v and 4 mhz at 3.0 v timebase clock automatically selected exte rnally, if external clock is available clock monitor for both internal and external clocks 7.3 functional description as shown in figure 7-1 , the icg contains these major submodules: clock enable circuit internal clock generator external clock generator clock monitor circuit clock selection circuit internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 68 freescale semiconductor figure 7-1. icg module block diagram internal to mcu external external clock generator extclken extxtalen ptb6 logic ptb7 logic ecgs osc1 ptb6 osc2 ptb7 internal clock generator osceninstop simoscen ibase icgs cmon clock monitor circuit eclk iclk clock selection circuit eoff ioff cgmxclk cs cgmout extslow clock/pin enable circuit icgon ecgon ecgen icgen dstg[7:0] tbmclk reset ddiv[3:0] ficgs name name name configuration (or mor) register bit register bit module signal n[6:0} trim[7:0] name top level signal functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 69 7.3.1 clock enable circuit the clock enable circuit is used to enable the internal clock (iclk) or external clock (eclk) and the port logic which is shared with the oscillator pins (o sc1 and osc2). the clock enable circuit generates an icg stop (icgstop) signal which stops all clocks (iclk, eclk, and the low-frequency base clock, ibase). icgstop is set and the icg is disabled in stop mode if the oscillator enable in stop (osceninstop) bit in the config (or mor) register is clear. the icg clocks will be enabled in stop mode if osceninstop is high. the internal clock enable signal (icgen) turns on the icg which generates iclk. icgen is set (active) whenever the icgon bit is set and the icgstop signa l is clear. when icgen is clear, iclk and ibase are both low. the external clock enable signal (ecgen) turns on the external clock generator which generates eclk. ecgen is set (active) whenever the ecgon bit is set and the icgstop signal is clear. ecgon cannot be set unless the external clock enable (extclken) bi t in the config (or mor) register is set. when ecgen is clear, eclk is low. the port b6 enable signal (pb6en) turns on the port b6 logic. since port b6 is on the same pin as osc1, this signal is only active (set) when the external clock function is not desired. therefore, pb6en is clear when ecgon is set. pb6en is not gated with icgstop, which means that if the ecgon bit is set, the port b6 logic will remain disabled in stop mode. the port b7 enable signal (pb7en) turns on the port b7 logic. since port b7 is on the same pin as osc2, this signal is only active (set) when two-pin oscillator function is not desired. therefore, pb7en is clear when ecgon and the external crystal enable (extxtalen) bit in the config (or mor) register are both set. pb6en is not gated with icgstop, which means that if ecgon and extxtalen are set, the port b7 logic will remain disabled in stop mode. 7.3.2 internal clock generator the icg, shown in figure 7-2 , creates a low frequency base clock (ibase), which operates at a nominal frequency (f nom ) of 307.2 khz 25%, and an internal clock (iclk) which is an integer multiple of ibase. this multiple is the icg multiplier factor (n), which is programmed in the icg multiplier register (icgmr). the icg is turned off and the output clocks (ibase and iclk) are held low wh en the icg enable signal (icgen) is clear. the icg contains: a digitally controlled oscillator a modulo "n" divider a frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators a digital loop filter internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 70 freescale semiconductor figure 7-2. internal clock generator block diagram 7.3.2.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk). the clock period of iclk is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because there is only a li mited number of bits in ddiv and dstg, the precision of the output (iclk) is restricted to a precision of approximately 0.202% to 0.368% when measured over several cycles (of the desired frequency). additionally, since the propagat ion delays of the devices used in the dco ring oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require alternately running faster and slower than desir ed, making the worst case cycle-to-cycle frequency variation 6.45% to 11.8% (of the desired frequency). the valid values of ddiv:dstg range from $000 to $9ff. for more information on the quantization error in the dco, see 7.4.4 quantization error in dco output . 7.3.2.2 modulo "n" divider the modulo "n" divider creates the low frequency base clock (ibase) by dividing the internal clock (iclk) by the icg multiplier factor (n), contained in the ic g multiplier register (icgmr). when n is programmed to a $01 or $00, the divider is disabled and iclk is passed thr ough to ibase undivided. when the icg is stable, the frequency of ibase will be equal to the nominal frequency (f nom ) of 307.2 khz 25%. 7.3.2.3 frequency comparator the frequency comparator effectiv ely compares the low frequency ba se clock (ibase) to a nominal frequency, f nom . first, the frequency comparator converts ibase to a voltage by charging a known capacitor with a current reference for a period dependent on ibase. this voltage is compared to a voltage digitally controlled oscillator iclk modulo "n" divider frequency comparator clock gen trim[7:0] voltage and current references ++ - - n[6:0] dstg[7:0] ficgs icgen ibase ddiv[3:0] name name name name config (or mor) register bit top level signal register bit module signal digital loop filter functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 71 reference with comparators, whose outputs are fed to the digital loop filter. the dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to 25% error in f nom . 7.3.2.4 digital loop filter the digital loop filter (dlf) uses the outputs of the frequency comparator to adjust the internal clock (iclk) clock period. the dlf generates the dco divider control bits (ddiv[3:0]) and the dco stage control bits (dstg[7:0]), which are fed to t he dco. the dlf first concatenates the ddiv and dstg registers (ddiv[3:0]:dstg[7:0]) and then adds or subtracts a value dependent on the relative error in the low frequency base clock?s period, as shown in table 7-1 . in some extreme error conditions, such as operating at a v dd level which is out of specification, the dlf may attempt to use a value above the maximum ($9ff) or below the minimum ($000). in both cases, the value for ddiv will be between $a and $f. in this range, the ddiv value will be interpret ed the same as $9 (the slowest condition). recovering from this condition requires subtracting (increasing frequency) in the normal fashion until the value is again below $9ff (if the desired value is $9xx, the value may settle at $axx through $fxx ? this is an acceptable operating condition). if the error is less than 15%, the icg?s filter stable indicator (ficgs) is set, indicating relative frequency accuracy to the clock monitor. all flash mask sets other than 0k45d, 1k45d, 0l09h, 1l09h have 15% comparators that improve stability at low temperatures. 7.3.3 external clock generator the icg also provides for an external oscillator or ex ternal clock source, if desired. the external clock generator, shown in figure 7-3 , contains an external oscillator am plifier and an external clock input path. 7.3.3.1 external oscillator amplifier the external oscillator amplifier prov ides the gain required by an external crystal connected in a pierce oscillator configuration. the amount of this gain is controlled by the slow external (extslow) bit in the config (or mor) register. when extslow is set, the amplifier gain is reduced for operating low-frequency crystals (32 khz to 100 khz). when extsl ow is clear, the amplifier gain will be sufficient for 1 mhz to 8 mhz crystals. extslow must be config ured correctly for the given crystal or the circuit may not operate. table 7-1. correction sizes from dlf to dco frequency error of ibase compared to f nom ddvi[3:0]:dstg[7:0] correction current to new ddiv[3:0]:dstg[7:0] (1) 1. x =maximum error is independent of value in ddiv[3:0]. ddiv increments or decrements when an addition to dstg[7:0] carries or borrows. relative correction in dco ibase < 0.85 f nom ?32 (?$020) minimum $xff to $xdf ?2/31 ?6.45% maximum $x20 to $x00 ?2/19 ?10.5% 0.85 f nom < ibase ibase < f nom ?1 (?$001) minimum $xff to $xfe ?0.0625/31 ?0.202% maximum $x01 to $x00 ?0.0625/17.0625 ?0.366% f nom < ibase ibase < 1.15 f nom +1 (+$001) minimum $xfe to $xff +0.0625/30.9375 +0.202% maximum $x00 to $x01 +0.0625/17 +0.368% 1.15 f nom < ibase +32 (+$020) minimum $xdf to $xff +2/29 +6.90% maximum $x00 to $x20 +2/17 +11.8% internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 72 freescale semiconductor figure 7-3. external clock generator block diagram the amplifier is enabled when the external clock generator enable (ecgen) signal is set and when the external crystal enable (extxtalen) bit in the config (or mor) register is set. ecgen is controlled by the clock enable circuit (see 7.3.1 clock enable circuit ), and indicates that the external clock function is desired. when enabled, the amplifier will be connected between the ptb6/(osc1) and ptb7/(osc2)/rst pins. otherwise, the ptb7/(osc2)/rst pin reverts to its port function. in its typical configuration, the external oscillator requires five external components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (included in the diagram to follow stri ct pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information.) 7.3.3.2 external clock input path the external clock input path is the means by which the microcontroller uses an external clock source. the input to the path is the ptb6/(osc1) pin and the output is the external clock (eclk). the path, which contains input buffering, is enabled when the exter nal clock generator enable signal (ecgen) is set. when not enabled, the ptb6/(osc1) pin reverts to its port function. c 1 c 2 r b x 1 r s * ecgen extxtalen eclk internal to mcu external osc1 ptb6 osc2 ptb7 amplifier input path extslow name name name name configuration (or mor) bit top level signal register bit module signal external clock generator *r s can be 0 (shorted) when used with higher- frequency crystals. refer to manufacturer?s data. these components are required for external crystal use only. functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 73 7.3.4 clock m onitor circuit the icg contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (eclk) and the internal clock (iclk) to dete rmine if either clock source has been corrupted. the clock monitor circuit, shown in figure 7-4 , contains these blocks: clock monitor reference generator internal clock activity detector external clock activity detector figure 7-4. clock monitor block diagram 7.3.4.1 clock monitor reference generator the clock monitor uses a reference based on one clock source to monitor the other clock source. the clock monitor reference generator generates the external reference clock (eref) based on the external clock (eclk) and the internal reference clock (iref) based on the internal clock (iclk). to simplify the circuit, the low frequency base clock (ibase) is used in place of iclk because it always operates at or extxtalen extslow ficgs ioff cmon ficgs ibase icgen eref ioff icgs ibase extxtalen extslow ecgs eclk ecgen icgon eref estbclk iref estbclk iref ecgen eclk cmon ecgs eoff cmon eoff ecgs icgs ibase icgen eclk ecgen iclk activity detector reference generator eclk activity detector name name name configuration (or mor) register bit register bit module signal name top level signal internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 74 freescale semiconductor near 307.2 khz. for proper operation, eref must be at least twice as slow as ibase and iref must be at least twice as slow as eclk. to guarantee that iref is slower than eclk and er ef is slower than ibase, one of the signals is divided down. which signal is divided and by how much is determined by the external slow (extslow) and external crystal enable (extxtalen) bits in the conf ig (or mor) register, according to the rules in table 7-2 . note each signal (ibase and eclk) is always divided by four. a longer divider is used on either ibase or eclk based on the extslow bit. to conserve size, the long divider (divide by 4096) is al so used as an external cr ystal stabilization divider. the divider is reset when the external clock generator is turned off or in stop (ecgen is clear). when the external clock generator is first turned on, the exte rnal clock generator stable bi t (ecgs) will be clear. this condition automatically selects eclk as the input to the long divider. the external stabilization clock (estbclk) will be eclk divided by 16 when extx talen is low or 4096 when extxtalen is high. this time-out allows the crystal to stabilize. the fa lling edge of estbclk is used to set ecgs (ecgs will set after a full 16 or 4096 cycles). when ecgs is set, th e divider returns to its normal function. estbclk may be generated by either ibase or eclk, but any cl ocking will only reinforce the set condition. if ecgs is cleared because the clock monitor determined that eclk was inactive, the divider will revert to a stabilization divider. since this will change the eref and iref divide ratios, it is important to turn the clock monitor off (cmon = 0) after inactivity is detected to ensure valid recovery. table 7-2. clock monitor reference divider ratios icgon ecgon ecgs extslow extxtalen external frequency eref divider ratio eref frequency estbclk divider ratio estbclk frequency iref divider ratio (1) 1. u = unaffected; refer to section of table where icgon or ecgon is set to 1. iref frequency 0xxxx u u u u u off 0 x 0 0 x x 0 off 0 off 0 u u 110x0 minimum 60 hz off 0 16 (eclk) 3.75 hz 1*4 76.8 khz 25% maximum 32 mhz 2.0 mhz 110x1 minimum 30 khz off 0 4096 (eclk) 7.324 khz 1*4 76.8 khz 25% maximum 8 mhz 1.953 khz 11100 minimum 307.2 khz 128*4 600 hz 16 (eclk) 19.2 khz 1*4 76.8 khz 25% maximum 32 mhz 62.5 khz 2.0 mhz 11101 minimum 1 mhz 128*4 1.953 khz 4096 (eclk) 244 hz 1*4 76.8 khz 25% maximum 8 mhz 15.63 khz 1.953 khz 11110 minimum 60 hz 1*4 15 hz 16 (ibase) (2) 2. ibase is always used as the internal frequency (307.2 khz). 19.2 khz 25% 4096*4 18.75 hz 125% maximum 307.2 khz 76.8 khz 11111 minimum 30 khz 1*4 7.5 khz 4096 (ibase) (2) 75 hz 25% 16*4 4.8 khz 25% maximum 100 khz 25.0 khz functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 75 7.3.4.2 internal clock activity detector the internal clock activity detector, shown in figure 7-5 , looks for at least one falling edge on the low-frequency base clock (ibase) every time the external reference (eref) is low. since eref is less than half the frequency of ibase, this should occur every time. if it does not occur two consecutive times, the internal clock inactivity indicator (ioff) is set. ioff will be cleared the next time there is a falling edge of ibase while eref is low. the internal clock stable bit (icgs) is also generated in the internal clock activi ty detector. icgs is set when the internal clock g enerator?s filter stable signal (ficgs) in dicates that ibase is within about 15% of the target 307.2 khz 25% for two consecutive measurements. icgs is cleared when ficgs is clear, the internal clock generator is turned off or in stop (icgen is clear), or when ioff is set. figure 7-5. internal clock activity detector 7.3.4.3 external clock activity detector the external clock activity detector, shown in figure 7-6 , looks for at least one fa lling edge on the external clock (eclk) every time the internal reference (iref) is low. since iref is less than half the frequency of eclk, this should occur every time. if it does not occur two consecutive times, the external clock inactivity indicator (eoff) is set. eo ff will be cleared the next time there is a falling edge of eclk while iref is low. the external clock stable bit (ecgs) is also generated in the external clock activity detector. ecgs is set on a falling edge of the external stabilization clock (estbclk). this will be 4096 eclk cycles after the external clock generator on bit is set or the mcu exit s stop (ecgen = 1) if the external crystal enable (extxtalen) in the config (or mor) register is set, or 16 cycles when extxtalen is clear. ecgs is cleared when the external clock generator is turned off or in stop (ecgen is clear) or when eoff is set. icgs ioff ibase r dq ck dffrr r icgen r d ck dffrs s q ck q 1/4 r ficgs eref cmon r dq ck dffrr r name name name name configuration (or mor) register bit top level signal register bit module signal dlf measure output clock internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 76 freescale semiconductor figure 7-6. external clock activity detector 7.3.5 clock se lection circuit the clock selection circuit, shown in figure 7-7 , contains two clock switches which generate the oscillator output clock (cgmxclk) and the timebase clock (tbmclk) from either the internal clock (iclk) or the external clock (eclk). the clock selection circuit also contains a divide-by-two circuit which creates the clock generator output clock (cgmout) , which generates the bus clocks. figure 7-7. clock selection circuit block diagram eggs eoff eclk r d q ck dffrr r estbclk r d ck dffrs s q ck q 1/4 r ecgen iref cmon name name name name configuration (or mor) register bit top level signal register bit module signal iclk eclk ioff eoff force_i force_e select output iclk eclk ioff eoff force_i force_e select output reset eclk eoff ecgon iclk ioff v ss cs div2 name name name name configuration (or mor) register bit top level signal register bit module signal synchronizing clock switcher synchronizing clock switcher cgmout cgmxclk tbmclk usage notes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 77 7.3.5.1 clock selection switches the first switch creates the oscillator output clock (cgm xclk) from either the internal clock (iclk) or the external clock (eclk), based on the clock select bi t (cs set selects eclk, clear selects iclk). when switching the cs bit, both iclk and eclk must be on (icgon and ecgon set). the clock being switched to must also be stable (icgs or ecgs set). the second switch creates the timebase clock (tbmclk) from iclk or eclk based on the external clock on bit. when ecgon is set, the switch automatically sele cts the external clock, regardless of the state of the ecgs bit. 7.3.5.2 clock switching circuit to robustly switch between the internal clock (iclk) and the external clock (eclk), the switch assumes the clocks are completely asynchr onous, so a synchronizing circuit is required to make the transition. when the select input (the clock select bit for the oscillator output clock switch or the external clock on bit for the timebase clock switch) is changed, the switch will continue to operate off the original clock for between 1 and 2 cycles as the select input is transitioned through one side of the synchronizer. next, the output will be held low for between 1 and 2 cycles of the new clock as the select input transitions through the other side. then the output starts switching at the new clock?s frequency. this transition guarantees that no glitches will be seen on the output even though the select input may change asynchronously to the clocks. the unpredictability of the transition per iod is a necessary result of the asynchronicity. the switch automatically selects iclk during reset. when the clock monitor is on (cmon is set) and it determines one of the clock sources is inactive (as indicated by the ioff or eoff signals), the circuit is forced to select the active clock. there are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected. however, the active side will not be selected until 1 to 2 clock cycles after the ioff or eoff signal transitions. 7.4 usage notes the icg has several features which can provide protection to the microcontroller if properly used. there are other features which can greatly simplify usage if certain techniques are employed. this subsection will describe several possible ways to use the icg and its features. these techniques are not the only ways to use the icg, and may not be optimum for all en vironments. in any case, these techniques should only be used as a template, and the user should modi fy them according to the application?s requirements. these notes include: switching clock sources enabling the clock monitor using clock monitor interrupts quantization error in dco output switching internal clock frequencies nominal frequency settling time improving frequency settling time trimming frequency internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 78 freescale semiconductor 7.4.1 switchin g clock sources switching from one clock source to another requi res both clock sources to be enabled and stable. a simple flow requires: 1. enable desired clock source 2. wait for it to become stable 3. switch clocks 4. disable previous clock source the key point to remember in this flow is that th e clock source cannot be switched (cs cannot be written) unless the desired clock is on and stable. a short assemb ly code example of how to employ this flow is shown in figure 7-8 . this code is for illustrative purposes only and does not represent valid syntax for any particular assembler. ;clock switching code example ;this code switches from internal to external clock ;clock monitor and interrupts are not enabled start lda #$13 ;mask for cs, ecgon, ecgs ; if switching from external to internal, mask is $0c. loop ** ** ;other code here, such as writing the cop, since ecgs may ; take some time to set sta icgcr ;try to set cs, ecgon and clear icgon. icgon will not ; clear until cs is set, and cs will not set until ; ecgon and ecgs are set. cmpa icgcr ;check to see if ecgs set, then cs set, then icgon clear bne loop ;keep looping until icgon is clear. figure 7-8. code example for switching clock sources 7.4.2 enabling the clock monitor many applications require the clock monitor to dete rmine if one of the clock sources has become inactive, so the other can be used to recover from a poten tially dangerous situation. using the clock monitor requires both clocks to be active (ecgon and icgon both set). to enable the clock monitor, both clocks must also be stable (ecgs and icgs both set). this is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable. enabling the clock monitor and clock monitor inte rrupts requires a flow similar to the one below: 1. enable the alternate clock source 2. wait for both clock sources to be stable 3. switch to the desired clock source if necessary 4. enable the clock monitor 5. enable clock monitor interrupts these events must happen in sequence. a short assembly code example of how to employ this flow is shown in figure 7-9 . this code is for illustrative purposes only and does not represent valid syntax for any particular assembler. usage notes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 79 ;clock monitor enabling code example ;this code turns on both clocks, selects the desired ; one, then turns on the clock monitor and interrupts start lda #$af ;mask for cmie, cmon, icgon, icgs, ecgon, ecgs ; if internal clock desired, mask is $af ; if external clock desired, mask is $bf ; if interrupts not desired mask is $2f int; $3f ext loop ** ** ;other code here, such as writing the cop, since ecgs ; and icgs may take some time to set. sta icgcr ;try to set cmie. cmie wont set until cmon set; cmon ; won?t set until icgon, icgs, ecgon, ecgs set. brset 6,icgcr,error ;verify cmf is not set cmpa icgcr ;check if ecgs set, then cmon set, then cmie set bne loop ;keep looping until cmie is set. figure 7-9. code example for enabling the clock monitor 7.4.3 using clock monitor interrupts the clock monitor circuit can be used to recover from pe rilous situations such as crystal loss. to use the clock monitor effectively, the following notes should be observed: enable the clock monitor and clock monitor interrupts. the first statement in the clock monitor interrupt service routine (cmisr) should be a read to the icg control register (icgcr) to verify the clock m onitor flag (cmf) is set. this is also the first step in clearing the cmf bit. the second statement in the cmisr should be a wr ite to the icgcr to clear the cmf bit (write the bit low). writing the bit high will not affect it. this statement does not n eed to immediately follow the first, but must be contained in the cmisr. the third statement in the cmisr should be to clear the cmon bit. this is required to ensure proper reconfiguration of the reference dividers. this statement must also be contained in the cmisr. although the clock monitor can only be enabled when both clocks are stable (icgs is set or ecgs is set), it will remain set if o ne of the clocks goes unstable. the clock monitor only works if the external slow (extslow) bit in the config (or mor) register is set to the correct value. the internal and external clocks must both be enabled and running in order to use the clock monitor. when the clock monitor detects inactivity, the inac tive clock is automatically deselected and the active clock selected as the source for cgmx clk and tbmclk. the cmisr can use the state of the cs bit to check which clock is inactive. when the clock monitor detects inactivity, t he application may have been subjected to extreme conditions which may have affected other circ uits. the cmisr should take any appropriate precautions. internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 80 freescale semiconductor 7.4.4 quantization error in dco output the digitally controlled oscillator (dco) is comprised of three major sub-blocks: binary weighted divider variable-delay ring oscillator ring oscillator fine-adjust circuit each of these blocks affects the clock period of the in ternal clock (iclk). since these blocks are controlled by the digital loop filter (dlf) outputs ddiv and dstg, the output of the dco can only change in quantized steps as the dlf increments or decrement s its output. the following subsections describe how each block will affect the output frequency. 7.4.4.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccu rate oscillator which generates the internal clock (iclk), whose clock period is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of the digital nature of the dco, the clock period of iclk will change in quantized steps. this will create a clock period difference, or quantization error (q-err) from one cycle to the next. over several cycles or for longer periods, this error is di vided out until it reaches a minimum error of 0.202% to 0.368%. the dependence of this error on the ddiv[3:0] value and the number of cycles the error is measured over is shown in table 7-3 . 7.4.4.2 binary weighted divider the binary weighted divider divides the output of the ring oscillator by a power of 2, specified by the dco divider control bits (ddiv[3:0]). ddiv maximi zes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. when ddiv is %0000, the ring oscillator?s output is divided by 1. incrementing ddiv by one will double the period; decrementing ddiv will halve the period. the dlf cannot directly increment or decrement ddiv; ddiv is only incremented or decremented when an addition or subtraction to dstg carries or borrows. table 7-3. quantization error in iclk ddiv[3:0] iclk cycles bus cycles iclk q-err %0000 (min) 1 na 6.45% ? 11.8% %0000 (min) 4 1 1.61% ? 2.94% %0000 (min) 32 8 0.202% ? 0.368% %0001 1 na 3.23% ? 5.88% %0001 4 1 0.806% ? 1.47% %0001 16 4 0.202% ? 0.368% %0010 1 na 1.61% ? 2.94% %0010 4 1 0.403% ? 0.735% %0010 8 2 0.202% ? 0.368% %0011 1 na 0.806% ? 1.47% %0011 4 1 0.202% ? 0.368% %0100 1 na 0.403% ? 0.735% %0100 2 1 0.202% ? 0.368% %0101 ? %1001 (max) 1 1 0.202% ? 0.368% usage notes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 81 7.4.4.3 variable-delay ring oscillator the variable-delay ring oscill ator?s period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three dco stage control bits (dstg[7:5]). a dstg[7:5] of %000 corresponds to 17 stage delays; dstg[7:5] of %111 corresponds to 31 stage delays. adjusting the dstg[5] bit has a 6.45% to 11.8% effect on the output frequency. this also corresponds to the size correction made when the frequency error is greater than 15%. the value of the binary weighted divider does not affect the relative change in output clock period for a given change in dstg[7:5]. 7.4.4.4 ring oscillator fine-adjust circuit the ring oscillator fine-adjust ci rcuit causes the ring oscillator to effectively operate at non-integer numbers of stage delays by operating at two different points for a variable number of cycles specified by the lower five dco stage control bits (dstg[4:0] ). for example, when dstg[7:5] is %011, the ring oscillator nominally operates at 23 stage delays. when ds tg[4:0] is %00000, the ring will always operate at 23 stage delays. when dstg[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles. like wise, when dstg[4:0] is %11111, the ring operates at 25 stage delays for 31 of 32 cycles and at 23 st age delays for one of 32 cycles. when dstg[7:5] is %111, similar results are achieved by including a vari able divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles. adjusting the dstg[0] bit has a 0.202% to 0.368% effect on the output clock period. this corresponds to the minimum size correction made by the dlf, and the inherent, long term quantization error in the output frequency. 7.4.5 switching in ternal clock frequencies the frequency of the internal clock (iclk) may need to be changed for some applications. for example, if the reset condition does not provide the correct freque ncy, or if the clock is slowed down for a low power mode (or sped up after a low-power mode), the freq uency must be changed by programming the internal clock multiplier factor (n). the frequency of iclk is n times the frequency of ibase, which is 307.2 khz 25%. before switching frequencies by changing the n val ue, the clock monitor must be disabled. this is because when n is c hanged, the frequency of the low-freq uency base clock (ibase) will change proportionally until the digital loop filter has corrected the error. since the clock monitor uses ibase, it could erroneously detect an inactive clock. the clock monitor cannot be re-enabled until the internal clock is stable again (icgs is set). the following flow is an example of how to change the clock frequency: verify there is no clock monitor interrupt by reading the cmf bit turn off the clock monitor if desired, switch to the external clock (see 7.4.1 switching clock sources ) change the value of n switch back to internal (see 7.4.1 switching clock sources ), if desired turn on the clock monitor (see 7.4.2 enabling the clock monitor ), if desired 7.4.6 nominal fr equency settling time because the clock period of the internal clock (iclk) is dependent on the digital loop filter outputs (ddiv and dstg) which cannot change instantaneously, iclk will temporarily operate at an incorrect clock internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 82 freescale semiconductor period when any of the operating condition changes. this happens whenever the part is reset, the icg multiply factor (n) is changed, the icg trim factor (trim) is changed, or the internal clock is enabled after inactivity (stop or disabl ed operation). the time that the iclk takes to adjust to the correct period is known as the settling time. settling time depends primarily on how many correcti ons it takes to change the clock period, and the period of each correction. since the corrections r equire four periods of the low-frequency base clock (4* ibase ), and since iclk is n (the icg multiply factor for the desired frequency) times faster than ibase, each correction takes 4*n* iclk . the period of iclk, however, will vary as the corrections occur. 7.4.6.1 settling to within 15% all flash mask sets other than 0k45d, 1k45d, 0l09h, 1l09h have 15% comparators that improve stability at low temperatures. when the error is greater than 15%, the filter takes eight corrections to double or halve the clock period. due to how the dco increases or decreases the clock period, the total period of these eight corrections is approximately 11 times the period of the fastest correct ion. (if the corrections were perfectly linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly nonlinear.) therefore, the total time it takes to double or halve the clock period is 44*n*t iclkfast . if the clock period needs more than doubled or halved, the same relationship applies, only for each time the clock period needs doubled, the total number of cycl es doubles. that is, when transitioning from fast to slow, going from the initial speed to half speed takes 44*n*t iclkfast ; from half speed to quarter speed takes 88*n*t iclkfast ; going from quarter speed to eighth speed takes 176*n*t iclkfast ; and so on. this series can be expressed as (2 x -1)*44*n*t iclkfast , where x is the number of times the speed needs doubled or halved. since 2 x happens to be equal to iclkslow / iclkfast , the equation reduces to 44*n*( iclkslow - iclkfast ). note increasing speed takes much longer than decreasing speed since n is higher. this can be expressed in te rms of the initial clock period ( 1 ) minus the final clock period ( 2 ) as such: once the clock period is within 15% of the desired cloc k period, the internal clock stable bit (icgs) will be set and the clock frequency is usable, al though the error will be as high as 15%. 7.4.6.2 total settling time once the clock period is within 15% of the desired clock period, the filter starts making minimum adjustments. in this mode, each correction will adjust the frequency between 0.202% and 0.368%. a maximum of 88 corrections will be required to get to the minimum error. each correction takes approximately the same period of time, or 4* ibase . this makes 88 corrections (352* ibase ) to get from 15% to the minimum error. the tota l time to the minimum error is: the equations for 15 , 5 , and tot are dependent on the actual initial and final clock periods 1 and 2 , not the nominal. this means the variability in the ic lk frequency due to process, temperature and voltage must be considered. additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. this mean s a worst case adjustment of up to 35% (iclk clock 15 abs 44n 1 2 ? () [] = tot abs 44n 1 2 ? () [] 352 ibase + = low-power modes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 83 period tolerance plus 10%) must be added. this adjustment can be reduced with trimming. table 7-4 shows some typical values for settling time. 7.4.7 trimming fr equency on the inter nal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, will vary as much as 25% due to process, temperature, and voltage dependencies. these dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. the voltage and temperature dependencies have been designed to be a maximum of approximately 1% error. the process dependencies account for the rest. fortunately, for an individual part, the process depend encies are constant. an individual part can operate at approximately 2% variance from its unadjusted operating poi nt over the entire spec range of the application. if the unadjusted operating point c an be changed, the entire variance can be limited to 2%. the method of changing the unadjusted operating point is by changing the size of the capacitor. this capacitor is designed with 639 equally sized units. 384 of these units are always connected. the remaining 255 units are put in by adjusting the icg trim factor (trim). the default value for trim is $80, or 128 units, making the default capacitor size 512. each unit added or removed will adjust the output frequency by about 0.195% of the unadjusted frequency (adding to trim will decrease frequency). therefore, the frequency of ibase can be changed to 25% of its unadjusted value, which is enough to cancel the process variability mentioned before. the best way to trim the internal clock is to use th e timer to measure the width of an input pulse on an input capture pin (this pulse must be supplied by the application and should be as long or wide as possible). considering the prescale value of the time r and the theoretical (zero error) frequency of the bus (307.2 khz *n/4), the error can be calculated. this e rror, expressed as a percentage, can be divided by 0.195% and the resultant factor added or subtracted from trim. this process should be repeated to eliminate any residual error. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the icg remains active in wait mode. if enabled, the icg interrupt to the cpu can bring the mcu out of wait mode. in some applications, low power consumption is desi red in wait mode and a high frequency clock is not needed. in these applications, reduce power consumpti on by either selecting a low-frequency external clock and turn the internal clock generator off, or reduce the bus frequency by minimizing the icg multiplier factor (n) before executing the wait instruction. table 7-4. typical settling time examples 1 2 n 15 tot 1/ (6.45 mhz) 1/ (25.8 mhz) 84 430 s 1165 s 1/ (25.8 mhz) 1/ (6.45 mhz) 21 107 s 840 s 1/ (25.8 mhz) 1/ (307.2 khz) 1 141 s 875 s 1/ (307.2 khz) 1/ (25.8 mhz) 84 11.9 ms 12.6 ms internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 84 freescale semiconductor 7.5.2 stop mode the value of the oscillator enable in stop (oscen instop) bit in the config (or mor) register determines the behavior of the icg in stop mode. if osceninstop is low, the icg is disabled in stop and, upon execution of the stop instruction, all ic g activity will cease and the output clocks (cgmxclk, cgmout, and tbmclk) will be held low. power consumption will be minimal. if osceninstop is high, the icg is enabled in stop and activity will continue. this is useful if the timebase module (tbm) is required to bring the mcu out of stop mode. icg interrupts will not bring the mcu out of stop mode in this case. during stop, if osceninstop is low, several functi ons in the icg are affected. the stable bits (ecgs and icgs) are cleared, which will enable the external clock stabilization divider upon recovery. the clock monitor is disabled (cmon = 0) whic h will also clear the clock monito r interrupt enable (cmie) and clock monitor flag (cmf) bits. the cs , icgon, ecgon, n, trim, ddiv, and dstg bits are unaffected. 7.6 config (or mor) register options there are four config (or mor) register options that affect the functionality of the icg. these options are: extclken (external clock enable) extxtalen (external crystal enable) extslow (slow external clock) osceninstop (oscillator enable in stop) all config (or mor) register options will have a default setting. 7.6.1 external cl ock enable (extclken) external clock enable (extclken), when set, enables the ecgon bit to be set. ecgon turns on the external clock input path through the ptb6/(os c1) pin. when extclken is clear, ecgon cannot be set and ptb6/(osc1) will alwa ys perform the ptb6 function. the default state for this option is clear. 7.6.2 external cryst al enable (extxtalen) external crystal enable (extxtalen), when set, will enable an amplifier to drive the ptb7/(osc2)/rst pin from the ptb6/(osc1) pin. the amplifier will only drive if the ex ternal clock enable (extclken) bit and the ecgon bit are also set. if extclken or ecgon are clear, ptb7/(osc2)/rst will perform the ptb7 function. when extxtalen is clear, ptb7/(osc2)/rst will always perform the ptb7 function. extxtalen, when set, also configures the clock monitor to expect an exte rnal clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external cl ock stabilization divider in the clock monitor for a 4096 cycle time-out to allow the pr oper stabilization time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles sinc e an external clock source does not need a start-up time. the default state for this option is clear. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 85 7.6.3 slow external clock (extslow) slow external clock (extslow), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 khz?100 khz) if properly enabled with the external clock enable (extclken) and external crystal enable (extxtalen) bits. when clear, extslow enables high-frequency crystal operation (1 mhz to 8 mhz). extslow, when set, also configures the clock monitor to expect an external clock source that is slower than the low-frequency base clock (60 hz?307.2 khz). when extslow is clear, the clock monitor will expect an external clock faster than the low-frequency base clock (307.2 khz?32 mhz). the default state for this option is clear. 7.6.4 oscillator enable in stop (osceninstop) oscillator enable in stop (oscenin stop), when set, will enable the icg to continue to generate clocks (either cgmxclk, cgmout, or tbmclk) in stop mo de. this function is used to keep the timebase running while the rest of the microcontroller stops . when osceninstop is clear, all clock generation will cease and cgmxclk, cgmout, and tbmclk will be forced low during stop. the default state for this option is clear. 7.7 i/o registers the icg contains five registers, summarized in figure 7-10 . these registers are: icg control register icg multiplier register icg trim register icg dco divider control register icg dco stage control register several of the bits in these registers have interacti on where the state of one bit may force another bit to a particular state or prevent another bit from being set or cleared. a summary of this interaction is shown in table 7-5 . addr. register name bit 7 6 5 4 3 2 1 bit 0 $0035 icg control register (icgcr) see page 87. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 1. see cmf bit description for method of clearing. $0037 icg multiplier register (icgmr) see page 88. read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 $0038 icg trim register (icgtr) see page 89. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 = unimplemented r = reserved u = unaffected figure 7-10. icg module i/o register summary internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 86 freescale semiconductor $0039 icg dco divider control register (icgdvr) see page 89. read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000uuuu icg dco stage control register (icgdsr) see page 89. read: dstg7 dstg6 dstg5 dst g4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr $003a reset: u u u u u u u u table 7-5. icg module register bit interaction summary condition register bit results for given condition cmie cmf cmon cs icgon icgs ecgon ecgs n [6:0] trim[7:0] ddiv[3:0] dstb[7:0] reset 0 0 0 0 1 0 0 0 $15 $80 ? ? osceninstop = 0, stop = 1 00 0?? 0 ? 0 ? ? ? ? extclken = 0 0 0 0 0 1 ? 0 0 ? ? uw uw cmf = 1 ? (1) 1 ? 1 ? 1 ? uw uw uw uw cmon = 0 0 0 (0) ? ? ? ? ? ? ? ? ? cmon = 1 ? ? (1) ? 1 ? 1 ? uw uw uw uw cs = 0 ? ? ? (0) 1 ? ? ? ? ? uw uw cs = 1 ? ? ? (1) ? ? 1 ? ? ? ? ? icgon = 0 0 0 0 1 (0) 0 1 ? ? ? ? ? icgon = 1 ? ? ??(1) ? ? ? ? ? uw uw icgs = 0 us ? us uc ? (0) ? ? ? ? ? ? ecgon = 0 0 0 0 0 1 ? (0) 0 ? ? uw uw ecgs = 0 us ? us us ? ? ? (0) ? ? ? ? ioff = 1 ? 1* (1) 1 (1) 0 (1) ? uw uw uw uw eoff = 1 ? 1* (1) 0 (1) ? (1) 0 uw uw uw uw n = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? trim = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? ?register bit is unaffected by the given condition. 0, 1register bit is forced clear or set (respectively) in the given condition. 0*, 1*register bit is temporarily forced clear or set (respectively) in the given condition. (0), (1)register bit must be clear or set (r espectively) for the given condition to occur. us, uc, uwregister bit cannot be set, cleared, or written (respectively) in the given condition. addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 7-10. icg module i/o register summary (continued) i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 87 7.7.1 icg c ontrol register the icg control register (icgcr) contains the contro l and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits. cmie ? clock monitor interrupt enable bit this read/write bit enables clock monitor interrupts. an interrupt will occur when both cmie and cmf are set. cmie can be set when the cmon bit has been set for at least one cycle. cmie is forced clear when cmon is clear or during reset. 1 = clock monitor interrupts enabled 0 = clock monitor interrupts disabled cmf ? clock monitor interrupt flag this read-only bit is set when the clock monitor deter mines that either iclk or eclk becomes inactive and the cmon bit is set. this bit is cleared by first re ading the bit while it is set, followed by writing the bit low. this bit is forced clear when cmon is clear or during reset. 1 = either iclk or eclk have become inactive 0 = iclk and eclk have not become inactive since th e last read of the icgcr, or the clock monitor is disabled cmon ? clock monitor on bit this read/write bit enables the clock monitor. cm on can be set when both iclk and eclk have been on and stable for at least one bus cycle (icgon, ecgon, icgs, and ecgs are all set). cmon is forced set when cmf is set, to avoid inadvertent clea ring of cmf. cmon is forced clear when either icgon or ecgon are clear, during stop with osceninstop low, or during reset. 1 = clock monitor output enabled 0 = clock monitor output disabled cs ? clock select bit this read/write bit determines which clock will gener ate the oscillator output clock (cgmxclk). this bit can be set when ecgon and ecgs have been set for at least one bus cycle and can be cleared when icgon and icgs have been set for at least one bus cycle. this bit is forced set when the clock monitor determines the internal clock (iclk) is inacti ve or when icgon is clear. this bit is forced clear when the clock monitor determines t hat the external clock (eclk) is inactive, when ecgon is clear, or during reset. 1 = external clock (eclk) sources cgmxclk 0 = internal clock (iclk) sources cgmxclk address: $0036 bit 7654321bit 0 read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 = unimplemented 1. see cmf bit description for method of clearing figure 7-11. icg control register (icgcr) internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 88 freescale semiconductor icgon ? internal clock generator on bit this read/write bit enables the internal clock generator. icgon can be cleared when the cs bit has been set and the cmon bit has been clear for at least one bus cycle. icgon is forced set when the cmon bit is set, the cs bit is clear, or during reset. 1 = internal clock generator enabled 0 = internal clock generator disabled icgs ? internal clock generator stable bit this read-only bit indicates when the internal clock generator has determined that the internal clock (iclk) is within about 15% of the desired value. this bit is forced clear when the clock monitor determines the iclk is inactive , when icgon is clear, when the icg multiplier register (icgmr) is written, when the icg trim register (icgtr) is written, during stop with osceninstop low, or during reset. 1 = internal clock is within 15% of the desired value 0 = internal clock may not be within 15% of the desired value ecgon ? external clock generator on bit this read/write bit enables the external clock generator. ecgon can be cleared when the cs and cmon bits have been clear for at least one bus cycl e. ecgon is forced set when the cmon bit or the cs bit is set. ecgon is forced clear during reset. 1 = external clock generator enabled 0 = external clock generator disabled ecgs ? external clock generator stable bit this read-only bit indicates when at least 4096 exter nal clock (eclk) cycles have elapsed since the external clock generator was enabled. this is not an assurance of the stability of eclk but is meant to provide a start-up delay. this bit is forced clear when the clock monitor determines eclk is inactive, when ecgon is clear, during stop with osceninstop low, or during reset. 1 = 4096 eclk cycles have elapsed since ecgon was set 0 = external clock is unst able, inactive, or disabled 7.7.2 icg multiplier register n6:n0 ? icg multiplier factor bits these read/write bits change the multiplier used by the internal clock generator. the internal clock (iclk) will be (307.2 khz 25%) * n. a value of $00 in this register is interpreted the same as a value of $01. this register cannot be wr itten when the cmon bit is set. reset sets this factor to $15 (decimal 21) for default frequency of 6.45 mhz 25% (1.613 mhz 25% bus). address: $0037 bit 7654321bit 0 read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 = unimplemented figure 7-12. icg multiplier register (icgmr) i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 89 7.7.3 icg trim register trim7:trim0 ? icg trim factor bits these read/write bits change the size of the internal capacitor used by the internal clock generator. by testing the frequency of the internal clock and increm enting or decrementing this factor accordingly, the accuracy of the internal clock can be improved to 2%. incrementing this register by one decreases the frequency by 0.195% of the unadjusted value. de crementing this register by one increases the frequency by 0.195%. this register cannot be written w hen the cmon bit is set. reset sets these bits to $80, centering the range of possible adjustment. 7.7.4 icg dco divider register ddiv3:ddiv0 ? icg dco divider control bits these bits indicate the number of divide-by-twos ( ddiv) that follow the digitally controlled oscillator. when icgon is set, ddiv is controlled by the digital loop filter. the range of valid values for ddiv is from $0 to $9. values of $a?$f are interpreted the same as $9. since the dco is active during reset, reset has no effect on dstg and the value may vary. 7.7.5 icg dco stage register address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 = unimplemented figure 7-13. icg trim register (icgtr) address: $0039 bit 7654321bit 0 read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu = unimplemented u = undefined figure 7-14. icg dco divider control register (icgdvr) address: $003a bit 7654321bit 0 read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset:uuuuuuuu = unimplemented r = reserved u = unaffected figure 7-15. icg dco stage control register (icgdsr) internal clock gene rator module (icg) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 90 freescale semiconductor dstg7:dstg0 ? icg dco stage control bits these bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. the total number of stages is approximately equal to $1ff, so changing dstg from $00 to $ff will approximately double the period. incrementing ds tg will increase the period (decrease the frequency) by 0.202% to 0.368% (decrementing has the opposite effect). dstg cannot be written when icgon is set to prevent inadvertent frequenc y shifting. when icgon is set, dstg is controlled by the digital loop filter. since t he dco is active during reset, reset has no effect on dstg and the value may vary. mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 91 chapter 8 external interrupt (irq) 8.1 introduction the external interrupt (irq) module provides a maskable interrupt input. 8.2 features features of the irq module include: a dedicated external interrupt pin (irq1 ) irq1 interrupt control bits internal pullup resistor hysteresis buffer programmable edge-only or edge- and level-interrupt sensitivity automatic interrupt acknowledge 8.3 functional description a logic 0 applied to the external interrupt pin can latch a central processor unit (cpu) interrupt request. figure 8-2 shows the structure of the irq module. interrupt signals on the irq1 pin are latched into the irq1 latch. an interrupt latch remains set until one of these actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a 1 to the ack1 bit clears the irq1 latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. the mode1 bit in the iscr controls the triggering sensitivity of the irq1 pin. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level triggered, the interrupt latch remains set until both of these occur: vector fetch or software clear return of the interrupt pin to logic 1 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 92 freescale semiconductor external interrupt (irq) figure 8-1. block diagram highlighting irq block and pins computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module irq1 pin mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 93 figure 8-2. irq block diagram the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask1 bit in the iscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask1 bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. 8.4 irq1 pin a logic 0 on the irq1 pin can latch an interrupt request into the irq1 latch. a vector fetch, software clear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 pin is both falling-edge sensitive an d low-level sensitive. with mode1 set, both of the following actions mu st occur to clear the irq1 latch: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt ackn owledge signal by writing a 1 to the ack1 bit in the interrupt status and control register (iscr). the ack1 bit is useful in applications that poll the irq1 pin and require software to clear the irq1 latc h. writing to the ack1 bit can also prevent spurious interrupts due to noise. setting ack1 d oes not affect subsequent transitions on the irq1 pin. a falling edge on the irq1 pin that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq1 pin to logic 1 ? as long as the irq1 pin is at logic 0, the irq1 latch remains set. ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 latch request irq1 v dd mode1 voltage detect irqf1 to cpu for bil/bih instructions vector fetch decoder internal address bus v dd internal pullup device synchronizer external interrupt (irq) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 94 freescale semiconductor the vector fetch or software clear and the return of the irq1 pin to logic 1 can occur in any order. the interrupt request remains pending as long as the irq1 pin is at logic 0. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq1 pin is falling-edge sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch. the irqf1 bit in the iscr can be used to check for pending interrupts. the irqf1 bit is not affected by the imask1 bit, which makes it useful in applications where polling is preferred. use the branch if interrupt pin is high (bih) or branch if interrupt pin is low (bil) instruction to read the logic level on the irq1 pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 8.5 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has these functions: shows the state of the irq1 interrupt flag clears the irq1 interrupt latch masks irq1 interrupt request controls triggering sensitivity of the irq1 interrupt pin irqf1 ? irq1 flag bit this read-only status bit is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ? irq1 interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq1 latch. ack1 always reads as 0. reset clears ack1. imask1 ? irq1 interrupt mask bit writing a 1 to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit controls the triggering sensitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt requests on falling edges and low levels 0 = irq1 interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf10 imask1 mode1 write:rrrrrack1 reset:0000u000 r = reserved u = unaffected figure 8-3. irq status and control register (iscr) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 95 chapter 9 keyboard interrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) provides five independently maskable external interrupt pins. 9.2 features kbi features include: five keyboard interrupt pins, on the mc68hc08kx8, are with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge-only or edge- and level-interrupt sensitivity automatic interrupt acknowledge exit from low-power modes figure 9-1. keyboard module block diagram kb0ie kb4ie or kb3ie . . . keyboard interrupt dq ck clr v dd modek imaskk keyboard interrupt ff request vector fetch decoder ackk internal bus reset to pullup kbd4 kbd0 to pullup synchronizer keyf enable enable or kbd3 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 96 freescale semiconductor keyboard interrupt module (kbi) figure 9-2. block diagram highlighting kbi block and pins computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3 ) pta3/kbd3 /tch1 (2), (3 ) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3 ) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 97 9.3 functional description writing to the kbie4?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control re gister (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) see page 99. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 100. read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-3. i/o register summary keyboard interrupt module (kbi) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 98 freescale semiconductor the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 9.4 keyboard initialization when a keyboard interrupt pin is enabled, the pin may initially be low and cause a false interrupt to occur. a false interrupt on an edge-triggered pin can be acknow ledged immediately after e nabling the pin. a false interrupt on an edge- and level-triggered interrupt pin must be acknowledged after the pin has been pulled high. the internal pullup device, the pin capacitance, as well as the external load will factor into the actual amount of time it takes for the pin to pull high. considering only an internal pullup of 48 k ? and pin capacitance of 8 pf, the pullup ti me will be on the order of 1 s. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddra bits in data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 9.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 9.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 99 9.6 i/o registers two registers control and monitor operation of the keyboard module: keyboard status and control register, kbscr keyboard interrupt enable register, kbier 9.6.1 keyboard status and contro l register the keyboard status and control register (kbscr): flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (kbscr) keyboard interrupt module (kbi) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 100 freescale semiconductor 9.6.2 keyboard inte rrupt enable register the keyboard interrupt enable register (kbier) enables or disables each port a pin to operate as a keyboard interrupt pin. kbie4?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = pax pin enabled as keyboard interrupt pin 0 = pax pin not enabled as keyboard interrupt pin address: $001b bit 7654321bit 0 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-5. keyboard interrupt enable register (kbier) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 101 chapter 10 low-voltage inhibit (lvi) 10.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 10.2 features features of the lvi module include: programmable lvi reset programmable power consumption selectable lvi trip voltage programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. lvistop, lvipwrd, lvi5or3, and lvirstd are user selectable options found in the configuration register (config1). see chapter 4 configuration register (config) . figure 10-1. lvi module block diagram the lvi is enabled out of reset. the lvi module c ontains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lv ipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvis top, enables the lvi to operate in stop mode. low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvitrip = 0 v dd lvitrip = 1 from config from config v dd from config lvirstd lvi5or3 from config low-voltage inhibit (lvi) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 102 freescale semiconductor setting the lvi 5-v or 3-v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. clearing the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip thresholds are specified in 17.5 5.0-vdc dc electrical characteristics and . note after a power-on reset, the lvi?s default mode of operation is 3 volts. if a 5-v system is used, the user must set the lvi5or3 bit to raise the trip point to 5-v operation. if the user requires 5-v mode and sets the lvi5or3 bit after power-on reset while the v dd supply is not above the v tripr for 5-v mode, the mcu will immediately go into reset. the next time the lvi releases the reset, the supply will be above the v tripr for 5-v mode. once an lvi reset o ccurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see chapter 13 system integration module (sim) for the reset recovery sequence. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr) and can be used for polling lvi operat ion when the lvi reset is disabled. 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvip wrd bit must be at 0 to enable the lvi module, and the lvirstd bit must be at 1 to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be at 0 to enable the lvi module and to enable lvi resets. 10.3.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 10.3.4 lvi trip selection the lvi5or3 bit in the configuration register selects whether the lvi is configured for 5-v or 3-v protection. note the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. see 17.5 5.0-vdc dc electrical characteristics and for the actual trip point voltages. lvi status register mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 103 10.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level while lvi resets have been disabled . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . the difference in these threshold levels results in a hysteresis that prevents oscillation into and out of reset. (see table 10-1 .) reset clears the lviout bit. 10.5 lvi interrupts the lvi module does not generate interrupt requests. 10.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.6.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.6.2 stop mode when the lvipwrd bit in the configuration register is cleared and the lvistop bit in the configuration register is set, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. address: $fe0c bit 7654321bit 0 read:lviout000000r write: reset:00000000 = unimplemented r = reserved figure 10-2. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value low-voltage inhibit (lvi) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 104 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 105 chapter 11 input/output (i/o) ports (ports) 11.1 introduction thirteen bidirectional input/output (i/o) pins form two parallel ports in the 16-pin plastic dual in-line package (pdip) and small outline integrated circuit (soic) package in the mc68hc908kx8 part. all i/o pins are programmable as inputs or outputs. port a has software selectable pullup resistors if the port is used as a general-function input port. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. see figure 11-1 for a summary of the i/o port registers. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 106. read: 0 0 0 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 108. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 106. read: 0 0 0 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 109. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $000d port a input pullup enable register (ptapue) see page 108. read: 0 0 0 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 = unimplemented figure 11-1. i/o port register summary input/output (i/o) ports (ports) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 106 freescale semiconductor 11.2 port a port a is a 5-bit special function port on the mc68hc908 kx8 that shares all of its pins with the keyboard interrupt module (kbi) and the 2-channel timer. port a contains software programmable pullup resistors enabled when a port pin is used as a general-function input. port a pins are also high-current port pins with 15-ma source/15-ma sink capabilities. 11.2.1 port a data register the port a data register (pta) contains a data latch for each of the five port a pins. pta4?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd4?kbd0 ? keyboard wakeup bits the keyboard interrupt enable bits, kbie4?kbie0, in the keyboard interrupt control register, enable the port a pins as external interrupt pins. see chapter 9 keyboard interrupt module (kbi) . tch1 and tch0 ? timer channel i/o bits the pta3/kbd3 /tch1 and pta2/kbd2 /tch0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb and elsxa, determine whether the pins are timer channel i/o pins or general-purpose i/o pins. see chapter 9 keyboard interrupt module (kbi) . 11.2.2 data dir ection register a data direction register a (ddra) determines whether eac h port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the co rresponding port a pin; a 0 disables the output buffer. address: $0000 bit 7654321bit 0 read: 0 0 0 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternate function: kbd4 kbd3 kbd2 kbd1 kbd0 alternate function: vrefh tch1 tch0 = unimplemented figure 11-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: 0 0 0 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 = unimplemented figure 11-3. data direction register a (ddra) port a mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 107 ddra4?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra4?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 11-4 shows the port a i/o logic. figure 11-4. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-1 summarizes the operation of the port a pins. 11.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) cont ains a software configur able pullup device for each of the five port a pins. each bit is individually c onfigurable and requires that the data direction register, ddra, bit be configured as an input. each pullup is automatically disabled when a port bit?s ddra is configured for output mode. table 11-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10x input, v dd (1) 1. i/o pin pulled up to v dd by internal pulllup device ddra4?ddra0 pin pta4?pta0 (2) 2. writing affects data register, but does not affect input. 0 0 x input, hi-z ddra4?ddra0 pin pta4?pta0 (3) x 1 x output ddra4?ddra0 pta4?pta0 pta4?pta0 x = don?t care hi-z = high impedance read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus v dd ptapuex internal pullup device input/output (i/o) ports (ports) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 108 freescale semiconductor ptapue4?ptapue0 ? port a input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port a pin configured to have internal pullup 0 = corresponding port a pin has internal pullup disconnected 11.3 port b port b is an 8-bit special-function port that shares four of its pins with the analog-to-digital converter module (adc), two with the serial communicati on interface module (sci) and two with an optional external clock source. 11.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port b pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. osc2 and osc1 ? osc2 and osc1 bits under software control, ptb7 and ptb6 can be configured as external clock inputs and outputs. ptb7 will become an output clock, osc2, if selected in the configuration registers and enabled in the icg registers. ptb6 will become an external input clock source, osc1, if selected in the configuration registers and enabled in the icg registers. see chapter 7 internal clock generator module (icg) and chapter 4 configuration register (config) . rxd ? sci receive data input bit the ptb1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the ptb1/rxd pin is available for general-purpose i/o. see chapter 12 serial communications interface module (sci) . address: $000d bit 7 6 5 4 3 2 1 bit 0 read: 0 0 0 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 = unimplemented figure 11-5. port a input pullup enable register (ptapue) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate function: osc2 osc1 txd rxd ad3 ad2 ad1 ad0 figure 11-6. port b data register (ptb) port b mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 109 txd ? sci transmit data output bit the ptb0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the ptb0/txd pin is available for general-purpose i/o. see chapter 12 serial communications interface module (sci) . ad3?ad0 ? analog-to-digital input bits ad3?ad0 are pins used for the input channels to t he analog-to-digital converter (adc) module. the channel select bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. see chapter 3 analog-to-digital converter (adc) . 11.3.2 data dir ection register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data directio n. reset clears ddrb7?ddrb0, configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 11-8 shows the port b i/o logic. figure 11-8. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 11-7. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output (i/o) ports (ports) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 110 freescale semiconductor when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-2 summarizes the operation of the port b pins. table 11-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x input, hi-z ddrb7?ddrb0 pin ptb7?ptb0 (1) 1. writing affects data register, but does not affect input. 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 x = don?t care hi-z = high impedance mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 111 chapter 12 serial communications interface module (sci) 12.1 introduction the serial communications interface (sci) allows as ynchronous communications with peripheral devices and other microcontroller unit (mcu). 12.2 features the sci module?s features include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format choice of baud rate clock source: ? internal bus clock ?cgmxclk 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter centra l processor unit (cpu) interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 112 freescale semiconductor serial communications interface module (sci) figure 12-1. block diagram highlighting sci block and pins computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module pin name conventions mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 113 12.3 pin name conventions the generic names of the sci input/output (i/o) pins are: rxd, receive data txd, transmit data sci i/o lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 12-1 shows the full names and the generic names of the sci i/o pins.the generic pin names appear in the text of this section. 12.4 functional description figure 12-3 shows the structure of the sci module. the sc i allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices , including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. the source of the baud rate clock is determined by the configuration register 2 bit, scibdsrc. if scibdsrc is set then the source of the sci is the internal data bus clock. if scibdsrc is cleared, the source of the sci is oscillator output cgmxclk. during normal operation, the cpu monito rs the status of the sci, writes the data to be transmitted, and processes received data. 12.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 12-2 . figure 12-2. sci data formats table 12-1. pin name conventions generic pin names rxd txd full pin names ptb4/rxd ptb5/txd bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 114 freescale semiconductor figure 12-3. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r 8 t 8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator rxd txd baudclk cgmxclk busclk a b s scibdsrc functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 115 12.4.2 transmitter figure 12-5 shows the structure of the sci transmitter. 12.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9- bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 12.4.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the tr ansmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) see page 125. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) see page 127. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) see page 129. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) see page 130. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) see page 132. read:000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) see page 133. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 133. read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 12-4. sci i/o register summary serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 116 freescale semiconductor figure 12-5. sci transmitter break characters at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of logic 1s. after the preamble shifts ou t, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port b pins. writing a 1 to the send break bit, sbk, in scc2 loads t he transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at 1, trans mitter logic conti nuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register fi nishes transmitting the last pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc baudclk parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 txd functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 117 break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. 12.4.2.3 break characters the sci recognizes a break character when a start bi t is followed by eight or nine 0 data bits and a 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception-in-progress flag (rpf) bits 12.4.2.4 idle characters an idle character contains all 1s and has no start, st op, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 12.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at 1. see 12.7.1 sci control register 1 . 12.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 118 freescale semiconductor 12.4.3 receiver figure 12-6 shows the structure of the sci receiver. figure 12-6. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 baudclk rxd functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 119 12.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 12.4.3.2 character reception during an sci reception, the receive shift register shi fts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 12.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 12-7 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 12-7. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 120 freescale semiconductor to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 12-2 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-3 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. table 12-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 12-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 121 to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-4 summarizes the results of the stop bit samples. 12.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. 12.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 12-8 shows how much a slow received characte r can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 12-8. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. table 12-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 122 freescale semiconductor with the misaligned character shown in figure 12-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 12-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycl es = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 12-9 shows how much a fast received characte r can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 12-9. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 12-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 12-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90%. = functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 123 the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 12.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: 1. address mark ? an address mark is a 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes th e receiver from the standby state by clearing the rwu bit. the address mark also sets the sc i receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. 2. idle input line condition ? when the wake bit is cl ear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 12.4.3.7 receiver interrupts these sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 12.4.3.8 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. 170 176 ? 170 ------------------------- - 100 3.53%. = serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 124 freescale semiconductor noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. 12.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 12.5.1 wait mode the sci module remains active in wait mode. an y enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 12.5.2 stop mode the sci module is inactive in stop mode. the stop in struction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 12.6 i/o signals port b shares two of its pins with the sci module. the two sci i/o pins are: txd ? transmit data rxd ? receive data 12.6.1 txd (transmit data) the txd pin is the serial data output from the sci tr ansmitter. the sci shares the txd pin with port b. when the sci is enabled, the txd pin is an output regardless of the state of the ddrb5 bit in data direction register b (ddrb). 12.6.2 rxd (receive data) the rxd pin is the serial data input to the sci receiver. the sci shares the rxd pin with port b. when the sci is enabled, the rxd pin is an input regardless of the state of the ddrb4 bit in data direction register b (ddrb). i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 125 12.7 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 12.7.1 sci cont rol register 1 sci control register 1 (scc1): enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 12-10. sci control register 1 (scc1) serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 126 freescale semiconductor txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit inverts all tran smitted values, including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether sci c haracters are eight or nine bits long. (see table 12-5 .) the ninth bit can serve as an extra stop bit, as a re ceiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wa kes up the sci: a 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit. 0 = idle character bit count begins after start bit. pen ? parity enable bit this read/write bit enables the sci parity function. (see table 12-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 12-2 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci gen erates and checks for odd parity or even parity. (see table 12-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 127 12.7.2 sci cont rol register 2 sci control register 2 (scc2): enables these cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to gener ate sci transmitter cpu interrupt requests. setting the sctie bit in scc3 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests table 12-5. character format selection control bits character format m pen?pty start bits data bits parity stop bits character length 0 0x 1 8none1 10 bits 1 0x 1 9none1 11 bits 0 10 1 7even1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8even1 11 bits 1 11 1 8 odd 1 11 bits address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 12-11. sci control register 2 (scc2) serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 128 freescale semiconductor scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generat e cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break c haracters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 129 12.7.3 sci cont rol register 3 sci control register 3 (scc3): stores the ninth sci data bit received and the ninth sci data bit to be transmitted. enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit characters, r8 is a co py of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. rese t has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented r = reserved u = unaffected figure 12-12. sci control register 3 (scc3) serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 130 freescale semiconductor peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled note bits 5 and 4 are reserved for mcus with a direct-memory access (dma) module. because the mc68hc908kx8 does not have a dma module, these bits should not be set. 12.7.4 sci status register 1 sci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt reques t. in normal operation, clear the scte bit by reading scs1 with scte set and then wr iting to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 12-13. sci status register 1 (scs1) i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 131 scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an id le condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 12-14 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is se t. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 132 freescale semiconductor figure 12-14. flag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 12.7.5 sci status register 2 sci status register 2 (scs2) contai ns flags to signal these conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading address: $0017 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 12-15. sci status register 2 (scs2) byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 133 the scdr. once cleared, bkf can become se t again only after 1s agai n appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception-in-progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the sci module or entering st op mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress 12.7.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading address $0018 accesses the read-only receiv ed data bits, r7?r0. writing to address $0018 writes the data to be transmitted, t7?t0. reset has no effect on the sci data register. note do not use read-modify-write instructions on the sci data register. 12.7.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 12-16. sci data register (scdr) address: $0019 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 12-17. sci baud rate register (scbr) serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 134 freescale semiconductor scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 12-6 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 12-7 . reset clears scr2?scr0. use this formula to calculate the sci baud rate: where: f baudclk = baud clock frequency pd = prescaler divisor bd = baud rate divisor table 12-8 shows the sci baud rates that can be generated with a 4.9152-mhz cgmxclk frequency. table 12-6. sci baud rate prescaling scp[1:0] prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 12-7. sci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f baudclk 64 pd bd ------------------------------------ = i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 135 table 12-8. sci baud rate selection examples scp[1:0] prescaler divisor (pd) scr[2:1:0] baud rate divisor (bd) baud rate (f baudclk = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 serial communications in terface modu le (sci) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 136 freescale semiconductor mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 137 chapter 13 system integration module (sim) 13.1 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. the sim is a system state controll er that coordinates the central processor unit (cpu) and exception timing. together with the cpu, the si m controls all microcontroller unit (mcu) activities. figure 13-1 is a summary of the sim input/output (i/o) registers. a block diagram of the sim is shown in figure 13-2 . the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources addr.register name bit 7654321bit 0 $fe01 sim reset status register (srsr) see page 148. read: por 0 cop ilop ilad menrst lvi 0 write: por:10000000 $fe04 interrupt status register 1 (int1) see page 149. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 150. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 150. read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 13-1. sim i/o register summary system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 138 freescale semiconductor figure 13-2. sim block diagram table 13-1 shows the internal signal names used in this section. table 13-1. signal name conventions signal name description cgmxclk selected clock source from internal clock generator module (icg) cgmout clock output from icg module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset (por) module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to icg) cgmout (from icg) internal clocks master reset control lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from icg) 2 forced mon mode entry (from menrst module) sim bus clock control and generation mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 139 13.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 13-3 . this clock originates from either an external oscillat or or from the internal clock generator. figure 13-3. system clock signals 13.2.1 bus timing in user mode , the internal bus frequency is the internal clock generator output (cgmxclk) divided by four. 13.2.2 clock startup fr om por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals ar e inactive and held in an inactive phase until after 4096 cgmxclk cycles. the mcu is held in reset by the sim during this entire period. the bus clocks start upon completion of the timeout. 13.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or rese t, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become ac tive until after the stop delay timeout. stop mode recovery timing is discussed in detail in 13.6.2 stop mode . in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. icg cgmxclk 2 bus clock generators sim icg sim counter monitor mode clock select circuit iclk cs 2 a b s* cgmout * when s = 1, cgmout = b user mode generator eclk system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 140 freescale semiconductor 13.3 reset and s ystem initialization the mcu has these internal reset sources: power-on reset (por) module computer operating properly (cop) module low-voltage inhibit (lvi) module illegal opcode illegal address forced monitor mode entr y reset (menrst) module all of these resets produce the vector $fffe?$ffff ($fefe?$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. these internal resets clear the sim counter and set a corresponding bit in the sim reset status register (srsr). see 13.4 sim counter and 13.7.1 sim reset status register . 13.3.1 active resets from internal sources an internal reset can be caused by an illegal addr ess, illegal opcode, cop timeout, lvi, por, or menrst as shown in figure 13-4 . note for lvi or por resets, the sim c ycles through 4096 cgmxclk cycles during which the sim asserts irst. the internal reset signal then follows with the 64-cycle phase as shown in figure 13-5 . the cop reset is asynchronous to the bus clock. figure 13-4. sources of internal reset figure 13-5. internal reset timing illegal address rst illegal opcode rst coprst lvi por internal reset menrst irst iab 64 cycles vector high cgmxclk reset and system initialization mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 141 13.3.1.1 power-on reset when power is first applied to the mcu, the power- on reset (por) module generates a pulse to indicate that power-on has occurred. the mcu is held in reset while the sim counter counts out 4096 cgmxclk cycles. another 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the internal clock generator. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. figure 13-6. por recovery 13.3.1.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the reset status register (srsr). to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12?5 of the sim counter. the sim counter output, which occurs at least every 2 12 ?2 4 cgmxclk cycles, drives the cop counte r. the cop should be serviced as soon as possible out of reset to guarantee the maximu m amount of time before the first timeout. the cop module is disabled if the irq1 pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high-voltage signal on the irq1 pin. this prevents the cop from becoming disabled as a result of external noise. 13.3.1.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. porrst cgmxclk cgmout irst iab 4096 cycles 64 cycles $fffe $ffff system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 142 freescale semiconductor if the stop enable bit, stop, in the configuration register (config1) is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. 13.3.1.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 13.3.1.5 forced monitor mode entry reset (menrst) the menrst module is monitoring the reset vector fetc hes and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode. see 16.3 monitor rom (mon) . 13.3.1.6 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v tripf voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config register are at 0. the mcu is held in reset until v dd rises above v tripr. the mcu remains in reset until the sim counts 4096 cgmxclk to begin a reset recovery. another 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. see chapter 10 low-voltage inhibit (lvi) . 13.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clock ed by the falling edge of cgmxclk. 13.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the internal clock generator to drive the bus clock state machine. 13.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt or reset, the sim senses the state of t he short stop recovery bit, ssrec, in the configuration register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. 13.4.3 sim counter and reset states the sim counter is free-running after all reset states. see 13.3.1 active resets from internal sources for counter control and internal reset recovery sequences. program exception control mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 143 13.5 program exception control normal, sequential program execution can be changed in two ways: 1. interrupts a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 13.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the return-from-interrupt (rti) instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 13-7 shows interrupt entry timing. figure 13-8 shows interrupt recovery timing. figure 13-7 . interrupt entry figure 13-8. interrupt recovery interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. as shown in figure 13-9 , once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the i bit is cleared. module idb r/ w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/ w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 144 freescale semiconductor figure 13-9. interrupt processing 13.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 13-10 demonstrates what happens when two interrupts are pending. if an interrupt no no no yes no yes no yes yes from reset i bit set? irq1 interrupt icg clk mon interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes i bit set? yes other interrupts no swi instruction rti instruction ? ? ? ? ? low-power modes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 145 is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the load-accumulator- from-memory (lda) instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m68hc05, m6805, and m146805 families the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. figure 13-10 . interrupt recognition example 13.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 13.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 13.6 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. low-power modes are exited via an interrupt or reset. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 146 freescale semiconductor 13.6.1 wait mode in wait mode, the cpu clocks are inactive while one set of peripheral clocks continues to run. figure 13-11 shows the timing for wait mode entry. figure 13-11. wait mode entry timing a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset. if the cop di sable bit, copd, in the configuration register is a 0, then the computer operating properly module (c op) is enabled and remains active in wait mode. figure 13-12 and figure 13-13 show the timing for wait recovery. figure 13-12. wait recovery from interrupt figure 13-13. wait recovery from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/ w note: previous data can be operand data or the wait opcode, depending on the last instruction. $de0c $de0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $de $a6 iab idb exitstopwait note: exitstopwait = cpu interrupt iab idb irst $a6 $a6 $de0b rst vct h rst vct l $a6 cgmxclk 64 cycles low-power modes mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 147 13.6.2 stop mode in stop mode, the sim counter is held in reset and the cpu and peripheral clocks are held inactive. if the osceninstop bit in the configuration register is not enabled, the sim also disables the internal clock generator module outputs (cgmout and cgmxclk). the cpu and peripheral clocks do not become acti ve until after the stop delay timeout. stop mode is exited via an interrupt request from a module that is still active in stop mode or from a system reset. an interrupt request from a module that is still active in stop mode can cause an exit from stop mode. stop recovery time is selectable using the ssrec bit in the configuration register. if ssrec is set, stop recovery is reduced from the normal delay of 4096 cg mxclk cycles down to 32. stacking for interrupts begins after the selected stop recovery time has elapsed. when stop mode is exited due to a reset condition, th e sim forces a long stop recovery time of 4096 cgmxclk cycles. note short stop recovery is ideal for applicat ions using canned oscillators that do not require long startup times for stop mode. external crystal applications should use the full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the executi on of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 13-14 shows stop mode entry timing. figure 13-14. stop mode entry timing figure 13-15. stop mode recovery from interrupt stop addr + 1 same same iab idb previous data next opcode same stop addr same r/ w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 148 freescale semiconductor 13.7 sim registers the sim has four memory mapped registers described here. 1. sim reset status register (srsr) 2. interrupt status register 1 (int1) 3. interrupt status register 2 (int2) 4. interrupt status register 2 (int3) 13.7.1 sim reset status register this register contains five bits that show the source of the last reset. the status register will clear automatically after reading it. a power-on reset sets t he por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr menrst ? forced monitor mode entry reset bit 1 = last reset was caused by the menrst circuit 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por 0 cop ilop ilad menrst lvi 0 write: por:10000000 = unimplemented figure 13-16. sim reset status register (srsr) sim registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 149 13.7.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. the interrupt sources and the interrupt status register flags that they set are summarized in table 13-2 . the interrupt status registers can be useful for debugging. 13.7.2.1 interrupt status register 1 if5?if1 ? interrupt flags 5, 4, 3, 2, and 1 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present table 13-2. interrupt sources source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag priority (2) 2. 0 = highest priority vector address swi instruction ? ? ? 0 $fffc?$fffd irq1 pin irqf1 imask1 if1 1 $fffa?$fffb icg clock monitor cmf cmie if2 2 $fff8?$fff9 tim channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim overflow tof toie if5 5 $fff2?$fff3 sci receiver overrun error or orie if11 6 $ffe6?$ffe7 sci receiver noise error nf neie sci receiver framing error fe feie sci receiver parity error pe peie sci receiver full scrf scrie if12 7 $ffe4?$ffe5 sci receiver idle idle ilie sci transmitter empty scte sctie if13 8 $ffe2?$ffe3 sci transmission complete tc tcie keyboard pins keyf imaskk if14 9 $ffe0?$ffe1 adc conversion complete ? aien if15 10 $ffde?$ffdf timebase module tbie tbf if16 11 $ffdc?$ffdd address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 13-17. interrupt status register 1 (int1) system integration module (sim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 150 freescale semiconductor if6 ? interrupt flag 6 since the mc68hc908kx8 parts do not use this interrupt flag, this bit will always read 0. bit 0 and bit 1 ? always read 0 13.7.2.2 interrupt status register 2 if14?if11 ? interrupt flags 14?11 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present if10?if7 ? interrupt flags 10?7 since the mc68hc908kx8 parts do not use these interrupt flags, these bi ts will always read 0. 13.7.2.3 interrupt status register 3 if22?if17 ? interrupt flags 22?17 since the mc68hc908kx8 parts do not use these interrupt flags, these bi ts will always read 0. if16?if15 ? interrupt flags 16?15 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 13-18. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 r= reserved figure 13-19. interrupt status register 3 (int3) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 151 chapter 14 timebase module (tbm) 14.1 introduction this section describes the timebase module (tbm). the tbm will generate periodic interrupts at user selectable rates using a counter clocked by either the in ternal or external clock sources. this tbm version uses 15 divider stages, eight of which are user selectable. 14.2 features features of the tbm module include: software configurable periodic interrupts with divide by 8, 16, 32, 64, 128, 2048, 8192, and 32,768 taps of the selected clock source configurable for operation during stop mode to allow periodic wake up from stop 14.3 functional description this module can generate a periodic interrupt by dividing the clock source supplied from the internal clock generator module, tbmclk. note that this clock sour ce is the external clock eclk when the ecgon bit in the icg control register (icgcr) is set. otherwise , tbmclk is driven at the internally generated clock frequency (iclk). in other words, if the external clock is enabled it will be used as the tbmclk, even if the mcu bus clock is based on the internal clock. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 14-1 , starts counting when the tbon bit is set. when the counter ov erflows at the tap selected by tbr2?tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the interrupt is generated at approximately half of the ov erflow period. subsequent events occur at the exact period. the timebase module may remain active after execution of the stop instruction if the internal clock generator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. 14.4 interrupts the timebase module can periodically interrupt the cpu with a rate defined by the selected tbmclk and the select bits tbr2?tbr0. when the timebase counter c hain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the c ounter chain overflow will generate a cpu interrupt request. interrupts must be acknowledged by writing a 1 to the tack bit. timebase module (tbm) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 152 freescale semiconductor figure 14-1. timebase block diagram 2 2 2 2 2 2 2 2 2 2 2 128 32,768 8192 2048 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbmint tbon 2 r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 64 32 16 tbmclk from icg module 8 tbm interrupt rate mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 153 14.5 tbm interrupt rate the interrupt rate is determined by the equation: where: f tbmclk = frequency supplied from the internal clock generator (icg) module divider = divider value as determined by tbr2?tbr0 settings. see table 14-1. as an example, a clock source of 4.9152 mhz and th e tbr2?tbr0 set to {011}, the divider tap is 128 and the interrupt rate calculates to 128/4.9152 x 10 6 = 26 s. note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). 14.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 14.6.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before executing the wait instruction. 14.6.2 stop mode the timebase module may remain active after execution of the stop instruction if the internal clock generator has been enabled to operate during stop mode through the osceninstop bit in the configuration register. the timebase module can be used in this mode to generate a periodic wake up from stop mode. if the internal clock generator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the ti mebase register is not accessible by the cpu. if the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before execut ing the stop instruction. table 14-1. timebase divider selection tbr2 tbr1 tbr0 divider tap 0 0 0 32768 0018192 0102048 011128 100 64 101 32 110 16 111 8 t tbmrate 1 f tbmrate ------------------------ divider f tbmclk -------------------- - == timebase module (tbm) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 154 freescale semiconductor 14.7 timebase control register the timebase has one register, the timebase control register (tbcr), which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when th e timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2?tbr0 ? timebase divider selection bits these read/write bits select the tap in the counter to be used for timebase interrupts as shown in table 14-1 . note do not change tbr2?tbr0 bits while the timebase is enabled (tbon = 1). tack? timebase acknowledge bit the tack bit is a write-only bit and always reads as 0. writing a 1 to this bit clears tbif, the timebase interrupt flag bit. writing a 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled bit this read/write bit enables the timebase interrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt is enabled. 0 = timebase interrupt is disabled. tbon ? timebase enabled bit this read/write bit enables the timebase. timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialized by clearing and then setting this bit. reset clears the tbon bit. 1 = timebase is enabled. 0 = timebase is disabled and t he counter initialized to 0s. address: $001c bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 14-2. timebase control register (tbcr) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 155 chapter 15 timer interface module (tim) 15.1 introduction this section describes the timer interface module (t im). the tim is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width modulation functions. figure 15-2 is a block diagram of the tim. 15.2 features features include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection free-running or modulo up-counter operation toggle either channel pin on overflow tim counter stop and reset bits 15.3 pin name conventions the tim shares two input/output (i/o) pins with two port a i/o pins. the full names of the tim i/o pins are listed in table 15-1 . the generic pin names appear in the text that follows. 15.4 functional description figure 15-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a mo dulo up-counter. the tim counter provides the timing reference for the input capture and output compare f unctions. the tim counter modulo registers, tmodh and tmodl, control the modulo value of the tim c ounter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels are programmable independently as input capture or output compare channels. figure 15-3 summarizes the timer registers. table 15-1. pin name conventions tim generic pin names: tch0 tch1 full tim pin names: pta2 /kbd2/tch0 pta3/kbd3/tch1 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 156 freescale semiconductor timer interface module (tim) figure 15-1. block diagram highlighting tim block and pins computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user flash ? 7680 bytes user ram ? 192 bytes monitor rom ? 295 bytes user flash vector space ? 36 bytes power internal bus v dd v ss pta ddra power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3 ) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2)/rst (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable time base module ptb6/(osc1) (4) flash burn-in rom ? 1024 bytes internal clock generator module system integration module irq module (software selectable) notes: 1. pin contains integrated pullup resistor 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. break module functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 157 figure 15-2. tim block diagram addr.register name bit 7654321bit 0 $0020 timer status and control register (tsc) see page 163. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (tcnth) see page 164. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer counter register low (tcntl) see page 164. read:bit 7654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (tmodh) see page 165. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 = unimplemented figure 15-3. tim i/o register summary prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a port tof toie inter- 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a logic rupt logic inter- rupt logic port logic inter- rupt logic pta2/kbd2 /tch0 pta3/kbd3 /tch1 timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 158 freescale semiconductor 15.4.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps2?ps0, in the tim status and control register select the tim clock source. 15.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter into the tim channel registers, tchxh and tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 15.4.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests. $0024 timer counter modulo register low (tmodl) see page 165. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (tsc0) see page 165. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (tch0h) see page 168. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer channel 0 register low (tch0l) see page 168. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (tsc1) see page 165. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer channel 1 register high (tch1h) see page 168. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (tch1l) see page 168. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 15-3. tim i/o register summary (continued) functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 159 15.4.4 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 15.4.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered ch anges in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.4.5 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the 1s written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 15.4.6 pulse-widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 15-4 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 160 freescale semiconductor to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin on overflow if the state of the pwm pulse is logic 0. the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 15.8.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50 percent. figure 15-4. pwm period and pulse width 15.4.7 unbuffered pw m signal generation any output compare channel can generate unbuffered pwm pulses as described in 15.4.6 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct period pulse width overflow overflow overflow output compare output compare output compare pt a x/tch functional description mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 161 in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 15.4.8 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the 1s written to last. tsc0 cont rols and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 15.4.9 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh and tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh and tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb and msxa. see table 15-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb and elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 15-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise . toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 162 freescale semiconductor 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h and tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is alr eady in and have no effect. the result is a 0 percent duty cycle output. setting the channel x maximum duty cycle bit (c hxmax) and setting the tovx bit generates a 100 percent duty cycle output. see 15.8.4 tim channel status and control registers . 15.5 interrupts these tim sources can generate interrupt requests: tim overflow flag (tof) ? the timer overflow fl ag (tof) bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow interrupt requests. tof and toie are in the tim status and control registers. tim channel flags (ch1f and ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu in terrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 15.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 15.6.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 15.6.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 15.7 i/o signals port a shares two of its pins with the tim, pta3/kbd3 /tch1 and pta2/kbd2 /tch0. each channel input/output (i/o) pin is programmable independently as an input capture pin or an output compare pin. tch0 can be configured as buffered output compare or buffered pwm pins. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 163 15.8 i/o registers these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim control registers (tcnth and tcntl) tim counter modulo registers (tmodh and tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h and tch0l, tch1h and tch1l) 15.8.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 15-5. tim status and control register (tsc) timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 164 freescale semiconductor trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps2?ps0 ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 15-2 shows. reset clears the ps2?ps0 bits. 15.8.2 tim counter registers the two read-only tim counter registers (tcnth and tcntl) contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim rese t bit (trst) also clears the tim counter registers. table 15-2. prescaler selection ps2?ps0 tim clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 not available register name and address: tcnth ? $0021 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 register name and address: tcntl ? $0022 bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented figure 15-6. tim counter registers (tcnth and tcntl) i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 165 15.8.3 tim counter modulo registers the read/write tim modulo registers (tmodh and tmodl) contain the modulo value for the tim counter. when the tim counter reaches the modulo value, th e overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. 15.8.4 tim channel status and control registers each of the tim channel status and control registers (tsc0 and tsc1): flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0 percent and100 percent pwm duty cycle selects buffered or unbuffered output compare/pwm operation register name and address: tmodh ? $0023 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 register name and address: tmodl ? $0024 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 15-7. tim counter modulo registers (tmodh and tmodl) register name and address: tsc0 ? $0025 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:0000000 0 register name and address: tsc1 ? $0028 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:0000000 0 = unimplemented figure 15-8. tim channel status and control registers (tsco and tsc1) timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 166 freescale semiconductor chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests 0 = channel x cpu interrupt requests disabled ms0b ? mode select bit b this read/write bit selects buffered output compare/pwm operation. ms0b exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and cont rol register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 15-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. see table 15-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the ms0b or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear , channel x is not connected to port a, and pin ptax/tchx is available as a general-purpose i/o pin. table 15-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. i/o registers mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 167 note before enabling a tim channel register for input capture operation, make sure that the ptax/tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 15-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100 percent duty cycle level until the cycle after chxmax is cleared. note the pwm 0 percent duty cycle is defined as output low all of the time. to generate the 0 percent duty cycle, select clear output on compare and then clear the tovx bit (chxmax = 0). the pwm 100 percent duty cycle is defined as output high all of the time. to generate the 100 percent duty cycle, use the chxmax bit in the tscx register. table 15-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 168 freescale semiconductor figure 15-9. chxmax latency 15.8.5 tim channel registers these read/write registers (tch0h/l and tch1h/l) contain the captured tim counter value of the input capture function or the output compare value of the ou tput compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. register name and address: tch0h ? $0026 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset register name and address: tch0l ? $0027 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset register name and address: tch1h ? $0029 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset register name and address: tch1l ? $002a bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 15-10. tim channel registers (tch0h/l and tch1h/l) output overflow period chxmax overflow overflow overflow overflow compare output compare output compare output compare pt a x/tch mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 169 chapter 16 development support 16.1 introduction this section describes the break module, the moni tor read-only memory (mon), and the monitor mode entry methods. 16.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software generated break interrupts computer operating properly (cop ) disabling during break interrupts 16.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu th en loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 16-1 shows the structure of the break module. 16.2.1.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 170 freescale semiconductor figure 16-1. break module block diagram 16.2.1.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 172. read:000100bw0 write:rrrrrrnoter reset:00010000 $fe03 sim break flag control register (sbfcr) see page 173. read: bcferrrrrrr write: reset: 0 $fe09 break address register high (brkh) see page 172. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 172. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 171. read: brke brka 000000 write: reset:00000000 $fe02 break auxiliary register (brkar) see page 173. read:0000000 bdcop write: reset:00000000 note: writing a 0 clears bw. = unimplemented r = reserved figure 16-2. i/o register summary iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break break module (brk) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 171 16.2.1.3 tim1 and tim2 during break interrupts a break interrupt stops the timer counters. 16.2.1.4 cop during break interrupts the cop is disabled during a break interrupt when b dcop bit is set in break auxiliary register (brkar). 16.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 16.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = when read, break address match 0 = when read, no break address match address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 16-3. break status and control register (brkscr) development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 172 freescale semiconductor 16.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. 16.2.2.3 break status register the break status register (sbsr) contains a flag to indicate that a break caus ed an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. bw ? break wait bit this read/write bit is set when a break interrupt caus es an exit from wait mode. clear bw by writing a 0 to it. reset clears bw. 1 = break interrupt during wait mode 0 = no break interrupt during wait mode bw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting 1 from it. address: $fe09 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 16-4. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 16-5. break address register low (brkl) address: $fe00 bit 7654321bit 0 read:000100bw0 write:rrrrrrnoter reset:00010000 note: writing a 0 clears bw. r = reserved figure 16-6. sim break status register (sbsr) break module (brk) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 173 16.2.2.4 break flag control register the break flag control register (sbfcr) contains a bi t that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 16.2.2.5 break auxiliary register the break auxiliary register (brkar) contains a bit that enables software to disable the cop while the mcu is in a state of break interrupt with monitor mode. bdcop ? break disable cop bit this read/write bit disables the cop during a break interrupt. reset clears the bdcop bit. 1 = cop disabled during break interrupt 0 = cop enabled during break interrupt 16.2.3 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.2.3.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set. clear the bw bit by writing 0 to it. 16.2.3.2 stop mode a break interrupt causes exit from stop mode and sets the bw bit in the break status register. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 16-7. sim break flag control register (sbfcr) address: $fe02 bit 7654321bit 0 read:0000000 bdcop write: reset:00000000 = unimplemented figure 16-8. break auxiliary register (brkar) development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 174 freescale semiconductor 16.3 monitor rom (mon) the monitor rom allows complete testing of t he microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry c an be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing hardware requirements for in-circuit programming. features include: normal user-mode pin functionality one pin dedicated to serial communicati on between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in random-a ccess memory (ram) or flash flash memory security (1) flash memory programming interface monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq 16.3.1 functional description the monitor rom receives and executes commands from a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the microcontroller unit (mcu) can execute host-computer code in ram while all mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configur ation and requires a pullup resistor. 16.3.1.1 monitor mode entry there are two methods for entering monitor mode. the first is the traditional m68hc08 method where v tst is applied to irq1 and the mode pins are configured appropriately. a second method, intended for in-circuit programming applications, will force entry into monitor mode without requiring high voltage on the irq1 pin when the reset vector locations of the flash are erased ($ff). both of these methods require that the pta1 pin be pulled low for the first 24 cgmxclk cycles after the part comes out of reset. this check is used by the monitor code to configure the mcu for serial communication. 16.3.1.2 normal monitor mode normal monitor mode is useful fo r mcu evaluation, factory testing, and development tool programming operation. figure 16-9 shows an example circuit used for normal monitor mode. table 16-1 shows the pin conditions for entering this mode. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. monitor rom (mon) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 175 figure 16-9. normal monitor mode circuit table 16-1. monitor mode entry $fffe/ $ffff irq1 pin ptb1 pin (ptxmod1) ptb0 pin (ptxmod0) pta1 pin pta0 pin cgmout bus frequency (f op ) x v tst 0 1 0 1 $ff blank v dd x x 0 1 + + + v dd v tst mc145407 mc74hc125 68hc908kx8 rst (ptb7/osc2) irq1 osc1 v ss v dd pta0 v dd 10 k ? 0.1 f 1 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 10 k ? 5 6 + ptb1 (ptxmod1) pta1 ( serial select) v dd 10 k ? ptb0 (ptxmod0) 9.8304-mhz canned oscillator 0.1 f cgmxclk 2 ----------------------------- cgmout 2 -------------------------- cgmxclk 2 ----------------------------- cgmout 2 -------------------------- development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 176 freescale semiconductor note pta1 = 0 and pta0 = 1 allow normal serial communications. pta1 = 1 allows parallel communications during security code entry. (for parallel communications, configure pta0 = 0 or pta0 = 1.) the mcu initially comes out of reset using the external clock for its clock source. this overrides the user mode operation of the oscillator circuits where the part comes up using the internally generated oscillator. running from an external clock allows the mc u, using an appropriate frequency clock source, to communicate with host software at standard baud rates. note while the voltage on irq1 is at v tst , the icg module is bypassed and the external square-wave clock becomes the clock source. dropping irq1 to below v tst will remove the bypass and the mcu will revert to the clock source selected by the icg (as determined by the settings in the icg registers). in normal monitor mode with v tst on irq1 , the mcu alters ptb7/(osc2)/rst to function as a rst pin. this is useful for testing the mcu. dropping irq1 voltage to below v tst will revert ptb7/(osc2)/rst to its user mode function. the computer operating properly (cop) module is disabled in normal monitor mode whenever v tst is applied to the irq1 pin. if the voltage on irq1 is less than v tst , the cop module is controlled by the copd configuration bit. 16.3.1.3 forced monitor mode if the voltage applied to the irq1 is less than v tst , the mcu will come out of reset in user mode. the menrst module is monitoring the rese t vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode without requiring high voltage on the irq1 pin. once out of reset, the monitor code is initially execut ing off the internal clock at its default frequency. the monitor code reconfigures the icg m odule to use the external square-wave clock source. switching to an external clock source allows the mcu, using an appropriate clock frequency, to communicate with host software at standard baud rates. the cop module is disabled in forced monitor mode. any reset other than a power-on reset (por) will automatically force the mc u to come back to the forced monitor mode. 16.3.1.4 monitor mode vectors monitor mode uses alternate vectors for reset and swi interrupts. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 16-2 shows vector differences between user mode and monitor mode. table 16-2. monitor mode vector relocation modes reset vector high reset vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd monitor $fefe $feff $fefc $fefd monitor rom (mon) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 177 16.3.1.5 data format the mcu waits for the host to send eight security bytes (see 16.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecutive 0s) to the hos t computer, indicating that it is ready to receive a command. communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 16-10. monitor data format 16.3.1.6 break signal a start bit (0) followed by nine 0 bits is a break signal . when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 16-11. break transaction 16.3.1.7 baud rate the communication baud rate is controlled by the cgmxclk frequency output of the internal clock generator module. 16.3.1.8 force monitor mode in forced monitor mode, the baud rate is fixed at cgmxclk/1024. a cmgxclk frequency of 4.9152 mhz results in a 4800 baud rate. a 9.8304-mhz frequency produces a 9600 baud rate. 16.3.1.9 normal monitor mode in normal monitor mode, the communication baud rate is controlled by the cgmxclk frequency output of the internal clock generator module. table 16-3 lists cgmxclk frequencies required to achieve standard baud rates. other standard baud rates can be accomplished using other clock frequencies. the internal clock can be used as the clock source by programming the internal clock generator registers however, monitor mode will always be entered usin g the external clock as the clock source. table 16-3. normal monitor mode baud rate selection cgmxclk frequency (mhz) baud rate 9.8304 9600 bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 178 freescale semiconductor 16.3.1.10 commands the monitor rom firmware uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. figure 16-12. read transaction figure 16-13. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes : 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 4 4 1 = echo delay, 2 bit times write write echo from host address high address high address low address low data data notes: 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 11 4 11 4 4 43, 4 1 = echo delay, 2 bit times monitor rom (mon) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 179 a brief description of each monitor mode command is given in table 16-4 through table 16-9 . table 16-4. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 16-5. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 16-6. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo from host data return data development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 180 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 16-7. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 16-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 16-9. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo data data from host readsp readsp echo from host sp return sp high low run run echo from host monitor rom (mon) mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 181 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 16-14. stack pointer at monitor mode entry 16.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. if flash is erased, the eight security byte values to be sent to the mcu are $ff, the unprogrammed state of the flash. during monitor mode entry, a reset must be asserted. pta1 must be held low during the reset and 24 cgmxclk cycles after the end of the reset. then the mcu will wait for eight security bytes on pta0. each byte will be echoed back to the host. see figure 16-15. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code fr om flash. security remains bypassed until a reset occurs. after any reset, security will be locked. to bypass security again, the host must resend the eight security bytes on pta0. if the received bytes do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading flash locations returns undefined data, and trying to execute code from flas h causes an illegal address reset. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 development support mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 182 freescale semiconductor figure 16-15. monitor mode entry timing after receiving the eight security bytes from the hos t, the mcu transmits a break character signalling that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 pta1 irst v dd 4096 + 64 cgmxclk cycles 24 cgmxclk cycles 256 cgmxclk cycles (one bit time) 1 4 1 1 2 1 break notes: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 4 = wait 1 bit time before sending next byte. 4 from host from mcu mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 183 chapter 17 electrical specifications 17.1 introduction this section contains electrical and timing specifications. 17.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 17.5 5.0-vdc dc electrical characteristics , and for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd , v ss , and pta0?pta4 i 15 ma maximum current for pins pta0?pta4 i pta0 ?i pta4 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ?55 to +150 c electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 184 freescale semiconductor 17.3 functional operating range 17.4 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to 125 c operating voltage range v dd 3.0 10% 5.0 10% v characteristic symbol value unit thermal resistance pdip (16 pins) soic (16 pins) ja 66 95 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 135 c 5.0-vdc dc electrica l characteristics mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 185 17.5 5.0-vdc dc elec trical characteristics characteristic (1) 1. v dd = 5.5 vdc to 4.5 vdc, v ss = 0 vdc, t a = ?40 c to +125 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage i load = ?2.0 ma, all i/o pins i load = ?10.0 ma, all i/o pins i load = ?15.0 ma, pta0?pta4 only v oh v dd ?0.4 v dd ?1.5 v dd ?0.8 ? ? ? ? ? ? v output low voltage i load = 1.6 ma, all i/o pins i load = 10.0 ma, all i/o pins i load = 15.0 ma, pta0?pta4 only v ol ? ? ? ? ? ? 0.4 1.5 0.8 v input high voltage ? all ports, irq1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage ? all ports, irq1 v il v ss ? 0.3 x v dd v v dd supply current run (3), (4) wait (4), (5) stop, 25 c (6) 3. run (operating) i dd measured using internal oscillator at its 32-mhz rate. v dd = 5.5 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports co nfigured as inputs. measured with all modules enabled. 4. all measurements taken with lvi enabled. 5. wait i dd measured using internal oscillator at its 1-mhz rate. all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 6. stop i dd is measured with no port pin sourcing current; all m odules are disabled. oscstopen option is not selected. i dd ? ? ? 15 2.2 0.8 25 5 1.75 ma ma a i/o ports hi-z leakage current (7) 7. pullups and pulldowns are disabled. i il ?10 ? +10 a input current i in ?10 ? +10 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (8) 8. maximum is highest vo ltage that por is guaranteed. v por 0?100mv por reset voltage (9) 9. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 v dd + 4.0 v low-voltage inhibit reset, trip falling voltage v tripf 3.90 4.25 4.50 v low-voltage inhibit reset, trip rising voltage v tripr 4.20 4.35 4.60 v low-voltage inhibit reset/recover hysteresis v hys ?100?mv pullup resistor pta0?pta4, irq1 r pu 24 ? 48 k ? electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 186 freescale semiconductor 17.6 3.0-vdc dc elec trical characteristics characteristic (1) 1. v dd = 3.3 to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +125 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage i load = ?0.6 ma, all i/o pins i load = ?4.0 ma, all i/o pins i load = ?10 ma, pta0?pta4 only v oh v dd ?0.3 v dd ?1.0 v dd ?0.6 ? ? ? ? ? ? v output low voltage i load = 0.5 ma, all i/o pins i load = 6.0 ma, all i/o pins i load = 10 ma, pta0?pta4 only v ol ? ? ? ? ? ? 0.3 1.0 0.6 v v v input high voltage ? all ports, irq1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage ? all ports, irq1 v il v ss ? 0.3 x v dd v v dd supply current run (3), (4) wait (4), (5) stop, 25 c (6) 3. run (operating) i dd measured using internal oscillator at its 16-mhz rate. v dd = 3.3 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports co nfigured as inputs. measured with all modules enabled. 4. all measurements taken with lvi enabled. 5. wait i dd measured using internal oscillator at its 1 mhz rate. all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 6. stop i dd is measured with no port pins sourcing current; all modules are disabled. i dd ? ? ? 5 1 0.65 10 2.5 1.25 ma ma a i/o ports hi-z leakage current (7) 7. pullups and pulldowns are disabled. i il ?10 ? +10 a input current i in ?10 ? +10 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (8) 8. maximum is highest vo ltage that por is guaranteed. v por 0?100mv por reset voltage (9) 9. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate r por 0.02 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit reset, trip falling voltage v tripf 2.45 2.60 2.70 v low-voltage inhibit reset, trip rising voltage v tripr 2.55 2.66 2.80 v low-voltage inhibit reset/recover hysteresis v hys ?60?mv pullup resistor pta0?pta4, irq1 r pu 24 ? 48 k ? internal oscillator characteristics mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 187 17.7 internal osc illator characteristics 17.8 external osc illator characteristics characteristic (1) 1. v dd = 5.5 vdc to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +125 c, unless otherwise noted symbol min typ max unit internal oscillator base frequency (2), (3) 2. internal oscillator is selectable through softwa re for a maximum frequency. actual frequency will be multiplier (n) x base frequency. 3. f bus = ( f intosc / 4) x n when internal clock source selected f intosc 230.4 307.2 384 khz internal oscillator tolerance f osc_tol ?25 ? +25 % internal oscillator multiplier (4) 4. multiplier must be chosen to limit the maximum bus frequen cy of 4 mhz for 2.7-v operation and 8 mhz for 4.5-v operation. n1?127? characteristic (1) 1. v dd = 5.5 to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +125 c, unless otherwise noted symbol min typ max unit external clock option (2) , (3) with icg clock disabled with icg clock enabled extslow = 1 (4) extslow = 0 (4) 2. setting extclken configuration option enables osc1 pin for external clock square-wave input. 3. no more than 10% duty cycle deviation from 50% 4. extslow configuration option configures external oscillator for a slow speed crystal and sets the clock monitor circuits of the icg module to expect an external clock frequency that is higher/lower than the internal oscillator base frequency, f intosc. f extosc dc (5) 60 307.2 k 5. some modules may require a minimum frequency greater th an dc for proper operation. see appropriate table for this information. ? ? ? 32 m (6) 307.2 k 32 m (6) 6. mcu speed derates from 32 mhz at v dd = 4.5 vdc to 16 mhz at v dd = 2.7 vdc. hz external crystal options (7) , (8) extslow = 1 (4) extslow = 0 (4) 7. setting extclken and extxtalen configuration options enables osc1 and osc2 pins for external crystal option. 8. f bus = ( f extosc / 4) when external clock source is selected. f extosc 30 k 1 m ? ? 100 k 8 m hz crystal load capacitance (9) 9. consult crystal vendor data sheet, see figure 7-3. external clock generator block diagram . c l ???pf crystal fixed capacitance (9) c 1 ? 2 x c l ?pf crystal tuning capacitance (9) c 2 ? 2 x c l ?pf feedback bias resistor (9) r b ?10?m ? series resistor (9), (10) 10. not required for high-frequency crystals r s ???m ? electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 188 freescale semiconductor 17.9 trimmed accuracy of the internal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, can vary as much as 25% due to process, temperature, and voltage. the trimming capability ex ists to compensate for process affects. the remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting). these affects are designed to be minimal, however variation does occur. better performance is seen at 3 v and lower settings of n. 17.9.1 2.7-volt to 3.3- volt trimmed internal clo ck generator characteristics 17.9.2 4.5-volt to 5.5- volt trimmed internal clo ck generator characteristics characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c ?40 c to 125 c 2. absolute value of variation in ic g output frequency, tr immed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ? ? 2.5 4.0 5.0 5.7 % variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.03 0.05 %/c variation over voltage (3), (5) 25 c ?40 c to 85 c ?40 c to 125 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? ? 0.5 0.7 0.7 2.0 2.0 2.0 %/v characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c ?40 c to 125 c 2. absolute value of variation in ic g output frequency, tr immed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ? ? 4.0 5.0 7.0 10.0 % variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.05 0.08 %/c variation over voltage (3), (5) 25 c ?40 c to 85 c ?40 c to 125 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? ? 1.0 1.0 1.0 2.0 2.0 2.0 %/v trimmed accuracy of the internal clock generator mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 189 figure 17-1 through figure 17-4 illustrate typical performance. the fo rmula for this variation of frequency is (measured-nominal)/nominal. figure 17-1 shows the variation in icg frequency for a part trimmed at nominal voltage and temperature across v dd and temperature for a 3-v application with multiply register (n) set to 1. figure 17-2 shows 5 v. figure 17-1. example of frequency variation across temperature, trimmed at nominal 3 volts, 25 c, and n = 1 figure 17-2. example of frequency variation across temperature, trimmed at nominal 3 volts, 25 c, and n = 104 -6.00% -4.00% -2.00% 0.00% 2.00% 4.00% 6.00% 2.7 3 3.3 2.7 0.00862069 -0.004310345 -0.021551724 -0.036637931 3 0.012931034 0 -0.023706897 -0.034482759 3.3 0.00862069 0 -0.019396552 -0.034482759 -40 25 85 125 -6.00% -4.00% -2.00% 0.00% 2.00% 4.00% 6.00% 2.7 3 3.3 2.7 0.021688017 -0.004114642 -0.035937247 -0.054665964 3 0.027728231 0 -0.033768445 -0.055436193 3.3 0.033525215 0.006019945 -0.032552294 -0.055456462 -40 25 85 125 electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 190 freescale semiconductor figure 17-3 and figure 17-4 shows n set to 104, hex 68, which corresponds to an icg frequency of 31.9 mhz or 7.9 mhz bus. figure 17-3. example of frequency variation across temperature, trimmed at nominal 5 volts, 25 c, and n = 1 figure 17-4. example of frequency variation across temperature, trimmed at nominal 5 volts, 25 c, and n = 104 -6.00% -4.00% -2.00% 0.00% 2.00% 4.00% 6.00% 4.5 5 5.5 4.5 0.015021459 0.002145923 -0.025751073 -0.036480687 5 0.015021459 0 -0.021459227 -0.034334764 5.5 0.012875536 0.006437768 -0.019313305 -0.030042918 -40 25 85 125 ,, -9.00% -4.00% 1.00% 6.00% 4.5 5 5.5 4.5 0.031595514 -0.001573799 -0.045660099 -0.073709584 5 0.045460884 0 -0.052393569 -0.076379066 5.5 0.042572265 -0.009064287 -0.047532721 -0.077255613 -40 25 85 125 analog-to-digital converte r (adc) characteristics mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 191 17.10 analog-to-digital co nverter (adc) characteristics characteristic symbol min max unit notes supply voltage v dd 2.7 5.5 v input voltages v adin 0 v dd v resolution b ad 88 bits absolute accuracy (1), (2) 1. one count is 1/256 of v dd . 2. v refh is shared with v dd . v refl is shared with v ss . a ad ?2.5 +2.5 counts 8 bits = 256 counts adc clock rate f adic 500 k 1.048 m hz t aic = 1/f adic, tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 ? t aic cycles conversion time t adc 16 17 t aic cycles sample time t ads 5? t aic cycles monotocity m ad guaranteed zero input reading z adi 00 ? hex v in = v ss full-scale reading f adi ?ff hex v in = v dd input capacitance c adi ? 20 pf not tested electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 192 freescale semiconductor 17.11 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clear- ing hven to 0. 1?? s flash cumulative program hv period t hv (3) 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv maximum. ?? 4ms flash endurance (4) 4. typical endurance was evaluated for this product family. for additional information on how freescale defines typical en- durance , please refer to engineering bulletin eb619. ? 10 k 100 k ? cycles flash data retention time (5) 5. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25c using the arrhenius equation. for additional information on how freescale defines typical data retention , please refer to engineering bulletin eb618. ? 15 100 ? years mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 193 chapter 18 ordering information and mechanical specifications 18.1 introduction this section contains ordering numbers fo r mc68hc908kx8 and mc68hc908kx2. refer to figure 18-1 for an example of the device numbering system. in addition, this section give s the package dimensions for: 16-pin plastic dual in-line package (case number 648d) 16-pin small outline package (case number 751g) 18.2 mc order numbers figure 18-1. device numbering system table 18-1. mc order numbers mc order number (1) 1. p = plastic dual in-line package dw = small outline package operating temperature range mc68hc908kx8cp mc68hc908kx8cdw ?40 c to +85 c mc68hc908kx8vp mc68hc908kx8vdw ?40 c to +105 c mc68hc908kx8mp mc68hc908kx8mdw ?40 c to +125 c mc68hc908kx2cp mc68hc908kx2cdw ?40 c to +85 c mc68hc908kx2vp mc68hc908kx2vdw ?40 c to +105 c mc68hc908kx2mp mc68hc908kx2mdw ?40 c to +125 c m c 6 8 h c 9 0 8 k x 8 x x x family package designator temperature range ordering information and mechanical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 194 freescale semiconductor 18.3 16-pin plastic dual in-line package (pdip) 18.4 16-pin small outline package (soic) dim min max min max millimeters inches a 0.740 0.760 18.80 19.30 b 0.245 0.260 6.23 6.60 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.050 0.070 1.27 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.120 0.140 3.05 3.55 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.015 0.035 0.39 0.88 notes: 1. dimensioning a nd tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimensions a and b do not include mold protrusion. 5. mold flash or protrusions shall not exceed 0.25 (0.010). 6. rounded corners optional. 18 16 9 -a- -b- f h 16 pl g s k c d -t- s b m 0.25 (0.010) a s t seating plane l m j d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 mc68hc908kx8 ? mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 195 appendix a mc68hc908kx2 a.1 introduction this appendix describes the differences between the mc68hc908kx8 and the mc68hc908kx2. a.2 functional description the mc68hc908kx2 flash memory is an array of 2,048 bytes with an additional 36 bytes of user vectors and one byte used for block protection. see figure a-1 . note an erased bit reads as a 1 and a programmed bit reads as a 0. the program and erase operations are facilitated thr ough control bits in the flash control register (flcr). see 2.6 flash control register . the flash is organized internally as an 8-word by 8-bit complementary metal-oxide semiconductor (cmos) page erase, byte (8-bit) program embedded flash memory. each page consists of 64 bytes. the page erase operation erases all words within a page. a page is composed of two adjacent rows. a security feature prevents viewing of the flash contents. (1) see 2.6 flash control register for a complete description of flash operation. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. mc68hc908kx2 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 196 freescale semiconductor $0000 $003f i/o registers (64 bytes) $fe00 reserved $fe01 sim reset status register (srsr) $fe02 reserved $0040 $00ff ram (192 bytes) $fe03 reserved $fe04 reserved $fe05 reserved $0100 $0fff unimplemented (3840 bytes) $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $1000 $13ff flash burn-in rom (1024 bytes) $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $1400 $f5ff unimplemented (57,856 bytes) $fe0c lvi status register (lvisr) $fe0d $fe1f unimplemented (19 bytes) $f600 $fdff user flash memory (2048 bytes) $fe20 $ff46 monitor rom (295 bytes) $ff47 $ff7d unimplemented (55 bytes) $ff7e flash block protect register (flbpr) $ff7f $ffdb unimplemented (93 bytes) $ffdc $ffff flash vectors (36 bytes) figure a-1. mc68hc908kx2 memory map mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 197 appendix b mc68hc08kx8 b.1 introduction this appendix describes the differences between t he read-only memory (rom) version (mc68hc08kx8) and the flash version (mc68hc908kx8) of the microcontroller. basically, the differences are: flash x rom module changes ? flash for rom substitution ? partial use of flash-related module configuration register programming wider range of operating voltage b.2 flash x rom module changes this subsection describes changes between the flash and rom modules. b.2.1 flash for rom substitution flash memory and flash supporting modules are replaced by rom memory, see figure b-1 . in figure b-1 , the user flash and user flash vector spac e are respectively substituted by user rom and user rom vector space. additionally, these modules and registers have been eliminated in the rom version: flash burn-in rom module ? auxiliary flash routine codes flash charge pump module ? high-voltage for flash programming menrst module ? helps erased flash parts programming, see 13.3.1.5 forced monitor mode entry reset (menrst) sim reset status register, bi t 2 ? refers to menrst. see 13.7.1 sim reset status register . menrst has no function in the rom version and reading this bit will return 0. flash test control register, fltcr flash control register, flcr flash block protect register, flbpr mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 198 freescale semiconductor mc68hc08kx8 figure b-1. m68hc08kx8 mcu block diagram computer operating properly module security module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 78 bytes user rom ? 7680 bytes user ram ? 192 bytes monitor rom ? 296 bytes user rom vector space ? 36 bytes power internal bus v dd v ss pta ddra notes: 1. pin contains integrated pullup resistor. 2. high-current source/sink pin 3. pin contains software selectable pullup resistor if general function i/o pin is configured as input. 4. pins are used for external clock source or crystal/ceramic resonator option. power-on reset module low-voltage inhibit module pta4/kbd4 (2), (3) pta3/kbd3 /tch1 (2), (3) pta2/kbd2 /tch0 (2), (3) pta1/kbd1 (2), (3) pta0/kbd0 (2), (3) irq1 (1) 2-channel timer interface module ptb ddrb ptb7/(osc2) (4) ptb5/txd ptb4/rxd ptb3/ad3 ptb2/ad2 ptb0/ad0 ptb1/ad1 keyboard interrupt module analog-to-digital converter module serial communication interface module programmable timebase module ptb6/(osc1) (4) internal clock generator module system integration module irq module software selectable single brkpt break module configuration register programming mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 199 b.2.2 partial use of flash-related module 16.3 monitor rom (mon) was written having flash as user memory and user vector space. mon functions are maintained for the rom version. mon will allow execution of code in random-access memory (ram) or rom and provide rom memory security (1) . the memory programming interface, though, will have no effect in rom version. an assumption that must be made for the rom version is that the reset vector will always have a value different from $0000, corresponding to the user code start address. for this reason, force entry into monitor mode, described in 16.3.1.1 monitor mode entry and in 16.3.1.3 forced monitor mode , is not applicable to the rom version. the menrst m odule has been eliminated from the rom version. the security function described in 16.3.2 security also applies to the user rom memory for the rom version. b.3 configuration register programming functionally, the terms mor (mask option registe r) and config (configuration register) can be used interchangeably. mor and config are equivalent si nce both define the same module functionality options through the registers bits. as a naming conv ention, though, configuration registers are named mor for a rom version and config for a flash version. some modules affected by the configuration register bits make reference to default values of these bits and have recommendation notes on programming them. for specific information see: flash ? 2.5 flash memory (flash) icg ? 7.6 config (or mor) register options lvi ? 10.3 functional description port ? 11.3.1 port b data register cop ? 5.4.7 copd (cop disable) and 5.4.8 coprs (cop rate select) config ? 4.2 functional description note the user must keep in mind that these notes are not entirely applicable to the mor found in the rom version. the mor bits can neither assume the described config default values after reset nor can they be modified later under user code control. while the mor is mask defined, and consequently unwritable, config can be written once after each reset. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the rom difficult for unauthorized users. mc68hc08kx8 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 200 freescale semiconductor note with the flash charge pump elim inated, mor2 bit 2 (originally pmpregd in config) has no effect. readi ng this bit will return 0. for a complete description of other configuration bits, refer to 4.2 functional description . address: $001e bit 7 6 5 4 3 2 1 bit 0 read: r lvi2 extxtalen extslow extclken 0 osceinstop scibdsrc write: reset: unaffected by reset r= reserved figure b-2. mask option register 2 (mor2) address: $001f bit 7 6 5 4 3 2 1 bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset: unaffected by reset figure b-3. mask option register 1 (mor1) electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 201 b.4 electrical specifications this subsection contains el ectrical and timing specifications for the mc68hc08kx8. b.4.1 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to b.4.4 5.0-vdc dc electrical characteristics , and for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd , v ss , and pta0?pta4 i 15 ma maximum current for pins pta0?pta4 i pta0 ?i pta4 25 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma storage temperature t stg ?55 to +150 c mc68hc08kx8 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 202 freescale semiconductor b.4.2 functional operating range b.4.3 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to 105 c operating voltage range v dd 3.0 10% 5.0 10% v characteristic symbol value unit thermal resistance pdip (16 pins) soic (16 pins) ja 66 95 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 125 c electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 203 b.4.4 5.0-vdc dc electrical characteristics characteristic (1) 1. v dd = 5.5 vdc to 4.5 vdc, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage i load = ?2.0 ma, all i/o pins i load = ?10.0 ma, all i/o pins i load = ?15.0 ma, pta0?pta4 only v oh v dd ?0.4 v dd ?1.5 v dd ?0.8 ? ? ? ? ? ? v output low voltage i load = 1.6 ma, all i/o pins i load = 10.0 ma, all i/o pins i load = 15.0 ma, pta0?pta4 only v ol ? ? ? ? ? ? 0.4 1.5 0.8 v input high voltage ? all ports, irq1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage ? all ports, irq1 v il v ss ? 0.3 x v dd v v dd supply current run (3), (4) wait (4), (5) stop, 25 c (4), (6) 3. run (operating) i dd measured using internal oscillator at its 32-mhz rate. v dd = 5.5 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports co nfigured as inputs. measured with all modules enabled. 4. all measurements taken with lvi enabled. 5. wait i dd measured using internal oscillator at its 1-mhz rate. all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 6. stop i dd is measured with no port pin sourcing current; all m odules are disabled. oscstopen option is not selected. i dd ? ? ? 16.6 1.9 0.8 20 5 1.75 ma ma a i/o ports hi-z leakage current (7) 7. pullups and pulldowns are disabled. i il ?10 ? +10 a input leakage current i in ?1.0 ? +1.0 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (8) 8. maximum is highest vo ltage that por is guaranteed. v por 0?100mv por reset voltage (9) 9. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 v dd + 4.0 v low-voltage inhibit reset, trip falling voltage v tripf 3.90 4.3 4.50 v low-voltage inhibit reset, trip rising voltage v tripr 4.00 4.4 4.60 v low-voltage inhibit reset/recover hysteresis v hys ?100?mv pullup resistor pta0?pta4, irq1 r pu 24 ? 48 k ? mc68hc08kx8 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 204 freescale semiconductor b.4.5 3.0-vdc dc electrical characteristics characteristic (1) 1. v dd = 3.3 to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage i load = ?0.6 ma, all i/o pins i load = ?4.0 ma, all i/o pins i load = ?10 ma, pta0?pta4 only v oh v dd ?0.3 v dd ?1.0 v dd ?0.6 ? ? ? ? ? ? v output low voltage i load = 0.5 ma, all i/o pins i load = 6.0 ma, all i/o pins i load = 10 ma, pta0?pta4 only v ol ? ? ? ? ? ? 0.3 1.0 0.6 v v v input high voltage ? all ports, irq1 v ih 0.7 x v dd ? v dd + 0.3 v input low voltage ? all ports, irq1 v il v ss ? 0.3 x v dd v v dd supply current run (3), (4) wait (4), (5) stop, 25 c (4), (6) 3. run (operating) i dd measured using internal oscillator at its 16-mhz rate. v dd = 3.3 vdc. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports co nfigured as inputs. measured with all modules enabled. 4. all measurements taken with lvi enabled. 5. wait i dd measured using internal oscillator at its 1 mhz rate. all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 6. stop i dd is measured with no port pins sourcing current; all modules are disabled. i dd ? ? ? 4.4 1 0.65 10 2.5 1.25 ma ma a i/o ports hi-z leakage current (7) 7. pullups and pulldowns are disabled. i il ?10 ? +10 a input leakage current i in ?1.0 ? +1.0 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (8) 8. maximum is highest vo ltage that por is guaranteed. v por 0?100mv por reset voltage (9) 9. maximum is highest vo ltage that por is possible. v por 0700800mv por rise time ramp rate r por 0.02 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit reset, trip falling voltage v tripf 2.4 2.60 2.70 v low-voltage inhibit reset, trip rising voltage v tripr 2.5 2.68 2.80 v low-voltage inhibit reset/recover hysteresis v hys ?80?mv pullup resistor pta0?pta4, irq1 r pu 24 ? 48 k ? electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 205 b.4.6 internal oscill ator characteristics b.4.7 external oscillator characteristics characteristic (1) 1. v dd = 5.5 vdc to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted symbol min typ max unit internal oscillator base frequency (2), (3) 2. internal oscillator is selectable through software for a ma ximum frequency. actual frequency will be multiplier (n) x base frequency. 3. f bus = (f intosc / 4) x n when internal clock source selected f intosc 230.4 320 384 khz internal oscillator tolerance f osc_tol ?25 ? + 25 % internal oscillator multiplier (4) 4. multiplier must be chosen to limit the maximum bus frequen cy of 4 mhz for 2.7-v operation and 8 mhz for 4.5-v operation. n1?127? characteristic (1) 1. v dd = 5.5 to 2.7 vdc, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted symbol min typ max unit external clock option (2) , (3) with icg clock disabled with icg clock enabled extslow = 1 (4) extslow = 0 (4) 2. setting extclken configuration option enables osc1 pin for external clock square-wave input. 3. no more than 10% duty cycle deviation from 50% 4. extslow configuration option configures external oscillator for a slow speed crystal and sets the clock monitor circuits of the icg module to expect an external clock frequency that is higher/lower than the internal oscillator base frequency, f intosc. f extosc dc (5) 60 307.2 k 5. some modules may require a minimum frequency greater th an dc for proper operation. see appropriate table for this information. ? ? ? 32 m (6) 307.2 k 32 m (6) 6. mcu speed derates from 32 mhz at v dd = 4.5 vdc to 16 mhz at v dd = 2.7 vdc. hz external crystal options (7) , (8) extslow = 1 (4) extslow = 0 (4) 7. setting extclken and extxtalen configuration options enables osc1 and osc2 pins for external crystal option. 8. f bus = (f extosc / 4) when external clock source is selected. f extosc 30 k 1 m ? ? 100 k 8 m hz crystal load capacitance (9) 9. consult crystal vendor data sheet, see figure 7-3. external clock generator block diagram . c l ???pf crystal fixed capacitance (9) c 1 ? 2 x c l ?pf crystal tuning capacitance (9) c 2 ? 2 x c l ?pf feedback bias resistor (9) r b ?10?m ? series resistor (9), (10) 10. not required for high-frequency crystals r s ???m ? mc68hc08kx8 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 206 freescale semiconductor b.4.8 trimmed accuracy of t he internal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, can vary as much as 25% due to process, temperature, and voltage. the trimming capability ex ists to compensate for process affects. the remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting). these affects are designed to be minimal, however variation does occur. better performance is seen at 3 v and lower settings of n. b.4.8.1 2.7-volt to 3.3- volt trimmed internal clock generator characteristics b.4.8.2 4.5-volt to 5.5- volt trimmed internal clock generator characteristics characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c 2. absolute value of variation in ic g output frequency, tr immed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ?1.55.0 % variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.03 0.05 %/c variation over voltage (3), (5) 25 c ?40 c to 85 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? 0.5 0.7 2.0 2.0 %/v characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c 2. absolute value of variation in ic g output frequency, tr immed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ?4.07.0 % variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.05 0.08 %/c variation over voltage (3), (5) 25 c ?40 c to 85 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? 1.0 1.0 2.0 2.0 %/v electrical specifications mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 freescale semiconductor 207 b.4.9 analog-to-digital c onverter (adc) characteristics b.4.10 memory characteristics characteristic symbol min max unit notes supply voltage v dd 2.7 5.5 v input voltages v adin 0 v dd v resolution b ad 88 bits absolute accuracy (1), (2) 1. one count is 1/256 of v dd . 2. v refh is shared with v dd . v refl is shared with v ss . a ad ?2.5 +2.5 counts 8 bits = 256 counts adc clock rate f adic 500 k 1.048 m hz t aic = 1/f adic, tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 ? t aic cycles conversion time t adc 16 17 t aic cycles sample time t ads 5? t aic cycles monotocity m ad guaranteed zero input reading z adi 00 ? hex v in = v ss full-scale reading f adi ?ff hex v in = v dd input capacitance c adi ? 20 pf not tested characteristic symbol min max units ram data retention voltage (1) 1. specification is char acterized but not tested. v rdr 1.3 ? v mc68hc08kx8 mc68hc908kx8 mc68hc908kx2 mc68hc08kx8 data sheet, rev. 2.1 208 freescale semiconductor how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc908kx8 rev. 2.1, 07/2005 |
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